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參數(shù)資料
| 型號： | VSC6511RC |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Rotary Switch; Contact Current Max:1.5A; No. of Poles:2; No. of Switch Positions:11; Indexing:30 ; No. of Decks:2; Switch Terminals:Solder Lug; Circuitry:SPDT; Mounting Type:Panel; Switch Features:30 degrees Indexing RoHS Compliant: Yes |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM,1 MM HEIGHT, EXPOSED PAD, TQFP-64 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 379K |
| 代理商： | VSC6511RC |
VITESSE
Advance Product Information
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
VSC6511
Page 16
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
4/10/00
G52311-0, Rev 2.0
D
Package Pin Descriptions
Figure 10: Pin Diagram
Table 9: Pin Identification
Pin #
Name
Description
2,3,4,6
7,8,9,11
12,13,47,46
45,43,42,41
40,38,37,36
D0-D3
D4-D7
D8-D11
D12-D15
D16-D19
INPUT/OUTPUT - TTL
Bidirectional data bus. In Serializer mode, this is a 20-bit input bus timed to
REFCLK. In Deserializer mode, this is a 20-bit output bus timed to RCLK. In
Reclocker and Cable Driver mode, several of these bits are defined as status
outputs.
50
64
24
MODE0
MODE1
SCREN
INPUT - TTL: Mode select inputs. See Table #2.
INPUT - TTL: When HIGH, enables scrambling in Serializer/Deserializer modes
D5
H
V
R
C
R
V
D4
VDDT
D7
D8
D9
M
I
V
M
V
V
I
T
S
D17
VDDT
D10
D16
D18
D19
VSST
D2
VDDT
D3
1
D13
V53
VSST
SIGDET
C
S
V
D6
CAP0
VSST
VSSA
S
V
V
S
F
LINE
D15
VDDT
D12
D11
O
D14
S
O
D1
D0
V
S
V
S
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
63
61
59
57
55
53
51
49
33
35
37
39
41
43
45
47
(Top View)
T
VSC6511
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