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參數(shù)資料
| 型號： | VSC6511RC |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Rotary Switch; Contact Current Max:1.5A; No. of Poles:2; No. of Switch Positions:11; Indexing:30 ; No. of Decks:2; Switch Terminals:Solder Lug; Circuitry:SPDT; Mounting Type:Panel; Switch Features:30 degrees Indexing RoHS Compliant: Yes |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM,1 MM HEIGHT, EXPOSED PAD, TQFP-64 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 379K |
| 代理商： | VSC6511RC |
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 7
4/10/00
VITESSE
Advance Product Information
VSC6511
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
G52311-0, Rev. 2.0
D
Features: Serializer Mode
1.
20 Bit TTL Interface @ 74.25 MHz
2.
On-chip Clock Multiplier Unit
3.
On-Chip Scrambler and NRZI Encoder with ENABLE
4.
CRC Generator with ENABLE
5.
2 or 4 user configurable 75ohm cable driver outputs
6.
Output Signal Detect indicators
7.
Buffered REFCLK output for easy clock distribution
8.
700 mW Typical Power
Description
The VSC6511 can be configured as a 20-bit HDTV Serializer using the MODE[1:0] pins. A 74.25 MHz
TTL REFCLK is multiplied by 20 in the Clock Multiplier Unit (CMU) to generate a 1.485 GHz bit rate clock.
The CMU aligns a divided-by-20 clock with REFCLK in order to latch the 20-bit TTL data bus D[19:0] into the
Input Register. When enabled by CRC being HIGH, the data is monitored for SAV/EAV and a CRC checksum is
calculated and inserted into the data stream at the appropriate point in each video line. The data is then scram-
bled and NRZI encoded, only if this stage is enabled by SCREN=HIGH. The data is then serialized and output
on the differential outputs, SDO0/SDO0 and SDO1/SDO1, which are compliant with the SMPTE 292M cable
driving specifications. The scrambler and NRZI encoder can be disabled by setting the TTL input, SCREN to
LOW. The SDO0/SDO0 output can be disabled and forced HIGH by setting the TTL input OE0 to LOW. Simi-
larly, the SDO1/SDO1 output can be disabled and forced HIGH by setting the TTL input OE1 to LOW.
Figure 3: Serializer Mode
REFCLK
74.25 MHz
Clock
Multiply
x20
1.485 GHz
RCLK
CRCEN
SCREN
D[19:0]
SDO0
SDO0
ISET0
OE1
SDO1
SDO1
ISET1
Serializer
Scrambler
NRZI Encoder
D Q
*
CRC Gen
CABLE DRIVER
OUTPUTS
OE0
/20
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