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參數(shù)資料
| 型號： | VSC6511RC |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Rotary Switch; Contact Current Max:1.5A; No. of Poles:2; No. of Switch Positions:11; Indexing:30 ; No. of Decks:2; Switch Terminals:Solder Lug; Circuitry:SPDT; Mounting Type:Panel; Switch Features:30 degrees Indexing RoHS Compliant: Yes |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM,1 MM HEIGHT, EXPOSED PAD, TQFP-64 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 379K |
| 代理商： | VSC6511RC |
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 17
4/10/00
VITESSE
Advance Product Information
VSC6511
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
G52311-0, Rev. 2.0
D
30
CRC
BIDIRECTIONAL - TTL: In Serializer Mode, CRC Generation is enabled when
this input is HIGH and disabled when LOW. In Deserializer Mode and
Deserializer/Reclocker Mode, this is an output which indicates a CRC error has
occurred.
OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an
output which, when HIGH, indicates that a FRAME synchronization event is on
D[0:19].
OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an
output which, when HIGH, indicates that a LINE synchronization event is on
D[0:19].
OUTPUT- TTL: Output which is HIGH during the Horizontal Blanking period
between EAV and SAV.
OUTPUT - TTL: When HIGH, indicates that a valid receive signal is present on
SDI/SDI and that the SMPTE-292M incoming data is greater than 500ppm from
20xREFCLK.
INPUT - Differential. Serial input to CRU.
OUTPUT - Differential. High Speed Cable Driver output.
Serial output from the Serializer, Reclocker or SDI/SDI input buffer.
Connect resistor to ground to set the output swing of SDO0, and SDO1
INPUT - TTL. Output enable pins for SDO0, and SDO1. Enabled when high for
each output.
INPUT - TTL. REFerence CLocK at 74.25 MHz. This is the input to the CMU and
times D(19:0) in Serializer Mode.
OUTPUT - TTL: Output clock. In Serializer and Reclocker Mode, this is a buffered
version of REFCLK. In Deserializer Mode, this is the recovered clock used to time
D(19:0).
OUTPUT - TTL. An analog signal detect output which, when HIGH, indicates
that the IP/IN input contains a valid SMPTE-292M amplitude signal.
Analog I/O: Loop Filter Capacitor, 0.1uF nominal, 3V swing maximum
TEST1, TEST2
INPUT - TTL. LOW for factory test, HIGH for normal operation.
INPUT - POWER: This power supply would normally be 3.3V. If 5V tolerance is
required, this pin should be connected to 5V supply.
VDDD
Power Supply. 3.3V Supply for digital logic.
VDDT
TTL I/O Power Supply.
VREF
Voltage Reference Input. If used, this is biased to 1.25V.
VDDA
Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to pin 15.
VSSP
Ground for High Speed Outputs
VSST
TTL I/O Ground
VSSA
Analog Ground Bypass to pin 18.
26
FRAME
34
LINE
27
HANC
25
1.001
21,22
SDI, SDI
56,54
60,58
SDO0, SDO0
SDO1, SDO1
52,62
ISET0, ISET1
53,61
OE0, OE1
29
REFCLK
31
RCLK
33
SIGDET
16,17
CAP0, CAP1
49,19
1
V53
20,23,28,57,51
5,10,39,44
63
18
55,59
14,32,35,48
15
Pin #
Name
Description
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