VIA Technologies, Inc.
Preliminary VT6304
10
VT6304 R
EGISTERS
Definitions and usage for each of the registers listed below are provided on this and the following pages:
3.
PHY
REGISTER MAP FOR THE CABLE ENVIRONMENT
address
0000b
0001b
0
1
2
Physical_ID
3
4
5
6
R
7
PS
RHB
IBR
Extended(7)
Max_speed
Contender
Gap_count
0010b
0011b
0100b
reserved
reserved
Jitter
Total_ports
Delay
Link_acti
ve
Resume_i
nt
Pwr_class
0101b
ISBR
Loop
Pwr_fail
Timeout
Port_even
t
Enab_acc
el
Enab_mul
ti
0110b
0111b
1000b
Reserved
Page_select
reserve
Register0(page_select)
Port_select
1111b
Register7(page_select)
3.1.
PHY
REGISTER FIELDS FOR THE CABLE ENVIRONMENT
size
type
Physical_ID
6
r
-
default description
The address of this node determined during self-identification. A value of 63
indicates a malconfigured bus; the link shall not transmit any packets.
When set to one, indicate that this node is the root.
Cable Power status.
Root hold-off bit. When set to one, instructs the PHY to attempt to become
the root during the next tree identify process.
Initiate bus reset. When set to one, instructs the PHY to initiate a bus reset
immediately (without arbitration). This bit causes assertion of the reset state
for 166 us and is self-clearing.
Used to configure the arbitration timer setting in order to optimize gap times
according to the topology of the bus. IEEE 1394-1995 4.3.6
constant value of seven
the number of ports implemented by this PHY
Indicates the maximum speed this PHY supports;
000 - 98.304 Mbit/s
001 - 98.304 and 196.608 Mbit/s
010 - ... and 393.216 Mbit/s
011 - ... and 786.43 Mbit/s
100 -
nd 1,572.864 Mbit/s
101 -
nd 3,145.728 Mbit/s
all other values are reserved for future definition
R
PS
RHB
1
1
1
r
r
rw
-
-
0
IBR
1
rw
0
Gap_count
6
rw
3F
Extended
Total_ports
Max_speed
3
5
3
r
r
r
7
3
010