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參數(shù)資料
| 型號(hào)： | VT6304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1394.A 4 PORT PHYSICAL LAYER CHIP |
| 中文描述： | 1394.A 4端口物理層芯片 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 126K |
| 代理商： | VT6304 |
VIA Technologies, Inc.
Preliminary VT6304
6
P
IN
D
ESCRIPTIONS
No.
Link-PHY Interface
82
Name
Type
Description
LINKON
O
Link on. Indicates the reception of a link-on packet or port event
occurs by asserting a 6.114 MHZ signal.
Link power status. LPS is connected to either the VDD supplying
the LINK or to a pulsed output that is active when the LINK is
powered for the purpose of monitoring the LINK power status.
Link request. LREQ is an input from the LINK that requests the
PHY to perform some service.
Link interface isolation control input. This terminal controls the
operation of output differentiation logic on the CTL[0-1] and
D[0-7] signals. If an optional isolation barrier is implemented
between the VT6304 and LLC the ISO_ pin should be tied low to
enable the differentiation logic. If no isolation barrier is
implemented, the ISO_ should be tied high to disable
differentiation logics.
Control
I/O.
the
CTLn
communications control signals between the PHY and LINK.
Data I/O. The D terminals are bidirectional and pass data
between the PHY and LINK.
83
LPS
I
57
LREQ
I
74
ISO_
I
60, 58
CTL[0-1]
I/O
terminals
are
bidirectional
70, 69,
68, 66,
65, 64,
62, 61
72
D[0-7]
I/O
SCLK
O
System clock. SCLK provides a 49.152 MHZ clock signal, which
is synchronized with the data transfers to the LINK.
Analog Interface
93,
10,
17, 22
92, 9 ,
16, 22
91, 8, 15,
21
90, 7, 14,
20
94,
11,
18, 23
XTPA[0-3]P
I/O
Twisted-pair cable A differential positive signal pins.
XTPA[0-3]M
I/O
Twisted-pair cable A differential negative signal pins.
XTPB[0-3]P
I/O
Twisted-pair cable B differential positive signal pins.
XTPB[0-3]M
I/O
Twisted-pair cable B differential negative signal pins.
XTPBIAS[0-
3]
I/O
Twisted-pair bias voltage supply. Provide 1.85V (typical) nominal
bias for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that the cable
connections is active. Hi-impedance during chip reset or power
down. Can be disabled via remote packets or software defined in
P1394a Draft 2.0. Each of these pin must be decoupled with a 1-uF
capacitor to ground.
Misc.
87
XCPS
I
CPS : Cable power status. CPS is normally connected to the
cable power through a 11 Kohm/1 KOhm volatge divider. This
circuit drivers an internal comparator that detects the presencce
of cable power.
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| VT6305 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI 1394 Host Controller |
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