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參數(shù)資料
| 型號(hào)： | VT6304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1394.A 4 PORT PHYSICAL LAYER CHIP |
| 中文描述： | 1394.A 4端口物理層芯片 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 126K |
| 代理商： | VT6304 |
VIA Technologies, Inc.
Preliminary VT6304
11
Delay
Link_active
4
1
R
rw
0
1
Worse case repeater delay, expressed as 144+(delay*20)ns.
Link enabled. Default value of one subsequent to a power reset. Otherwise
cleared or set by software to control the value of the L bit transmitted in the
self-ID packet. The transmitted L bit shall be the logical AND of this bit and
the LPS signal.
Contender. Cleared or set by software to control the value of the C bit
transmitted in the self-ID packet.
Contender
1
rw
Pin
C/LKO
N
Pin
PC0-
PC2
Pwr_class
3
rw
Power class. Controls the value of the pwr field transmitted in the self-ID
packet.
000 - Node does not need power and does not repeat power
001 - Node is self-powered and provides a minimum of 15 W to the
bus
010 - Node is self-powered and provides a minimum of 30 W to the
bus.
011 - Node is self-powered and provides a minimum of 45 W to the
bus
100 - Node may be powered from the bus and is using up to 1 W.
101 - Node is powered from the bus and is using up to 1 W. An
additional 2 W is needed to enable the link and higher layers.
110 - Node is powered form the bus and is using up to 1 W. An
additional 5 W is needed to enable the link and higher layers.
111 - Node is powered from the bus and is using up to 1 W. An
additional 9 W is needed to enable the link and higher layers.
Jitter
3
R
0
The difference between the fastest and slowest repeater data delay, expressed
as (jitter+1)*20ns
Resume interrupt enable. When set to one, the PHY shall set port_event to
one if resume operations commence for any port.
Initiate short (arbitrated) bus reset. A write of one to this bit instructs the
PHY to arbitrate and issue a short bus reset. This bit is self-clearing.
Loop detect. A write of one to this bit clears it to zero.
Cable power failure detect. Set to one when the PS bit changes from one to
zero. A write of one to this bit clears it to zero.
Arbitration state machine timeout. A write of one to this bit clears it to zero.
Port event detect. The PHY sets this bit to one if any of connected, Bias,
Disabled or Fault change for a port whose Int_enable bit is one. The PHY
also sets this bit to one if resume operations commence for any port and
Resume_int is one. A write of one to this bit clears it to zero.
Enable arbitration acceleration. When set to one, the PHY shall use the
enhancements specification in P1394A.
Enable multi-speed packet concatenation. When set to one, the Link shall
signal the speed of all packets to the PHY.
Selects which of eight possible PHY register pages are accessible through
the window at PHY register address 1000b through 1111b, inclusive.
If the page selected by Page_select presents per port information, this field
selects which port’s registers are accessible through the window at PHY
Resume_int
1
Rw
0
ISBR
1
rw
0
Loop
Pwr_fail
1
1
rw
rw
0
0
Timeout
Port_event
1
1
rw
rw
0
0
Enab_accel
1
rw
0
Enab_multi
1
rw
0
Page_select
3
rw
000
Port_select
4
rw
0000
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PDF描述 |
|---|---|
| VT6305 | PCI 1394 Host Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VT6305 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI 1394 Host Controller |
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| VT6510B | 制造商:VIA 功能描述: |
| VT6516 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16/12 PORT 10/1000 ASE T/TX |
| VT-6-6 | 制造商:Panduit Corp 功能描述:BOLT TERM 70MM 57MM - Bulk 制造商:Panduit Corp 功能描述:Bolt Terminal 70mm 57mm |
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