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參數(shù)資料
| 型號： | VT6304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1394.A 4 PORT PHYSICAL LAYER CHIP |
| 中文描述： | 1394.A 4端口物理層芯片 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 126K |
| 代理商： | VT6304 |
VIA Technologies, Inc.
Preliminary VT6304
12
register addressed 1000b through 1111b, inclusive.
3.2.
PHY
REGISTER PAGE
0: P
ORT
S
TATUS PAGE
The port Status page is used to access configuration and status information for each of the
PHY’s port. The port is selected by writing zero to Page_select and the desired port number
to Port_select in the PHY register at address 0111.
0
1
2
3
1000b
AStat
BStat
1001b
Negotiated_speed
Int_enable
1010b
1011b
1100b
1101b
1110b
1111b
4
5
6
7
Child
Fault
connected
Bias
Disabled
3.3.
PHY
REGISTER PORT STATUS PAGE FIELDS
Size
Type
Astat
2
r
default
-
Description
TPA line State for the port
00 = invalid
01 =1
10 =0
11 =z
(same encoding as Astat)
If equal to one, the port is a child, else a parent. The meaning of this
bit is undefined from the time a bus reset is detected until the PHY
transitions to state T1:Child Handshake during the tree identify
process(see 4.4.2.2 in IEEE Std 1394-1995)
If equal to one, the port is connected, else disconnected. The value
reported by this bit is filtered by hysteresis logic to reduce multiple
status changes caused by contact scrape when a connector is inserted
or removed.
If equal to one, bias voltage is detected( possible connection). The
value reported by this bit is filtered by hysteresis logic to reduce
multiple status changes caused by contact scrape when a connector is
inserted or removed.
When set to one, the port shall be disabled. The value of this bit
subsequent to a power reset is implementation-dependent, but should
be a strappable option.
Indicated the maximum speed negotiated between this PHY port and
its immediately connected port; the encoding is
000 – 98.304Mbit/s
001 - and 196.608 Mbit/s
Bstat
Child
2
1
r
r
-
-
Conncted
1
r
0
Bias
1
r
-
Disabled
1
rw
0
Negotiated_sp
eed
3
r
-
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