
VIA Technologies, Inc.
Preliminary VT6304
3
VT6304 IEEE 1394
A
F
OUR
P
ORT
C
ABLE
T
RANSCEIVER
/A
RBITER
F
EATURES
n
Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the P1394a
Supplement 2.0.
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Full P1394a Supplement Support includes:
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Arbitrated short reset,
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Connection Debounce,
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Multispeed Concatenation,
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Ack Accelerated Arbitration,
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Fly-By Concatenation,
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Programmable Port Disable, Suspend, Resume,
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PHY IDs Do Not Increment Past 63
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Provides Four 1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbit/s)
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Single 3.3 V power supply
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Logic Performs Bus Initialization and Arbitration Functions
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Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding
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Incoming Data Resynchronized to Local Clock.
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Data Interface to Link-Layer Controller Provided Through 2/4/8 Parallel Lines at 49.152 MHz
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24.576 MHZ Crystal Oscillator and PLL Provide TX/RX Data at 100/200/400 Mbps and Link-Layer
Controller Clock at 49.152 MHZ.
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Cable Power Presence Monitoring.
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Programable Node Power Class Information for System Power Management
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Embedded Bus Holder Isolation to Link Layer Controller Interface
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Optional On-chip Resistors to Reduce Component Counts for Electrical Isolation to Link Layer
Controller Interface
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Fully Compliant P1394a 2.0 PHY Map
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Separate TPBIAS for Each Port
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Fully Interoperable with IEEE Std1394-1995 Devices
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Cable Ports Monitor Line Conditions for Active Connection to Remote Node
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Low Power Design for Battery-Powered Applications includes: User Controlled Power-Down via PD,
Automatic Device Power-Down during All Ports Suspended and Link Interface Disabled, Link
Interface Power-Down via Inactive LPS, Automatic Inactive Ports Powered-Down, and Automatic
Inactive Logic Power-Down
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Self Power Up Reset and Pinless PLL to Reduce Component Counts on System
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Low Cost 100-Pin PQFP package