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WESTERN DESIGN CENTER
W65C816S
March 1, 2000
18
2.13
Reset (RESB)
The Reset input is used to initialize the microprocessor and start program execution. The Reset input
buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pullup device.
The RESB signal must be held low for at least two clock cycles after VDD reaches operating voltage.
Ready (RDY) has no effect while RESB is being held low. The stack pointer must be initialized by the
user's software. During the Reset conditioning period, the following period, the following processor
initialization takes place:
Registers
D=0000
DBR=00
PRB=00
SH=01
XH=00
YH=00
N
V
M
X
D
I
Z
C/E
P =
*
*
1
1
0
1
*
*/1
*=not initialized
STP and WAI instructions are cleared.
Signals
E=1
MX=1
RWB=1
VDA=0
VPB =1
VPA=0
When Reset is brought high, an interrupt sequence is initiated:
RWB remains in the high state during the stack address cycles.
The Reset vector address is 00FFFC,D.
2.14
Valid Data Address and Valid Program Address (VDA and VPA)
These two output signals indicate valid memory addresses when high and must be used for memory
or I/O address qualification.
VDA
0
0
1
1
VPA
0
1
0
1
Internal Operation-Address and Data Bus available. The Address Bus may be invalid.
Valid program address-may be used for program cache control.
Valid data address-may be used for data cache control.
OpCode fetch-may be used for program cache control and single step control
2.15
VDD and VSS
VDD is the positive supply voltage and VSS is system logic ground.
2.16
Vector Pull (VPB)
The Vector Pull output indicates that a vector location is being addressed during an interrupt sequence.
VPB is low during the last two interrupt sequence cycles, during which time the processor reads the
interrupt vector. The VPB signal may be used to select and prioritize interrupts from several sources by
modifying the vector addresses.