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WESTERN DESIGN CENTER
W65C816S
March 1, 2000
3
TABLE OF CONTENTS
INTRODUCTION
................................................................................................................. 1
SECTION 1 W65C816S FUNCTIONAL DESCRIPTION
................................................. 2
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
Instruction Register and Decode....................................................................... 2
Timing Control Unit......................................................................................... 2
Arithmetic and Logic Unit................................................................................ 2
Internal Registers............................................................................................. 2
Accumulators................................................................................................... 2
Data Bank Register.......................................................................................... 3
Direct............................................................................................................... 3
Index................................................................................................................ 3
Processor Status............................................................................................... 3
Program Bank Register.................................................................................... 3
Program Counter.............................................................................................. 4
Stack Pointer.................................................................................................... 4
Figure 1-1 W65C816S Internal Architecture Simplified Block Diagram........... 5
Figure 1-2 W65C816S Microprocessor Programming Model........................... 6
Figure 1-3 W65C816S Status Register Coding................................................ 6
SECTION 2
PIN FUNCTION DESCRIPTION
...................................................... 7
Figure 2-1 W65C816S 44 Pin PLCC Pinout.................................................... 7
Figure 2-2 W65C816S 40 Pin PDIP Pinout..................................................... 8
Figure 2-3 W65C816S 44 PIN QFP Pinout..................................................... 9
Table 2-1 Pin Function Table.......................................................................... 10
Abort ............................................................................................................. 10
Address Bus.................................................................................................... 10
Bus Enable...................................................................................................... 11
Data/Address Bus............................................................................................ 11
Emulation Status............................................................................................. 11
Interrupt Request............................................................................................ 11
Memory Lock................................................................................................. 11
Memory/Index Select Status............................................................................ 11
Non-Maskable Interrupt.................................................................................. 12
Phase 2 In....................................................................................................... 12
Read/Write...................................................................................................... 12
Ready.............................................................................................................. 12
Reset............................................................................................................... 13
Valid Data Address and Valid Program Address.............................................. 13
VDD and VSS................................................................................................ 13
Vector Pull...................................................................................................... 13
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16