參數(shù)資料
型號: W9412G2IB-4
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 4M X 32 DDR DRAM, 0.6 ns, PBGA144
封裝: 12 X 12 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-144
文件頁數(shù): 8/50頁
文件大小: 826K
代理商: W9412G2IB-4
W9412G2IB
Publication Release Date: Aug. 30, 2010
- 16 -
Revision A06
7.10.1 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4, 8 words.
A2
A1
A0
BURST LENGTH
0
Reserved
0
1
2 words
0
1
0
4 words
0
1
8 words
1
x
Reserved
7.10.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both
addressing Mode support burst length 2, 4 and 8 words.
A3
ADDRESSING MODE
0
Sequential
1
Interleave
Addressing Sequence of Sequential Mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
Addressing Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
2 words (address bits is A0)
Data 1
n + 1
not carried from A0 to A1
Data 2
n + 2
4 words (address bit A0, A1)
Data 3
n + 3
Not carried from A1 to A2
Data 4
n + 4
Data 5
n + 5
8 words (address bits A2, A1 and A0)
Data 6
n + 6
Not carried from A2 to A3
Data 7
n + 7
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