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參數(shù)資料
| 型號： | W942508BH |
| 英文描述： | DRAM |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 12/45頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | W942508BH |
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W942508BH
- 12 -
(8)
V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set
equal to V
REF
and must track variations in the DC level of V
REF
.
These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between V
IH
min.(AC) and V
IL
max.(AC).Transition (rise and fall) of input signals have
a fixed slope.
(11) IF the result of nominal calculation with regard to t
CK
contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., t
DQSS
= 0.75
×
t
CK
, T
ck
= 7.5 nS, 0.75
×
7.5 nS = 5.625 nS is rounded up to 5.6 nS.)
(12) V
X
is the differential clock cross point voltage where input timing measurement is referenced.
(13) V
ID
is magnitude of the difference between CLK input level and
CLK
input level.
(14) V
ISO
means {V
ICK
(CLK)+V
ICK
(
CLK
)}/2.
(15) Refer to the figure below.
(9)
CLK
CLK
V
SS
V
ICK
V
X
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ID(AC)
V
ID(AC)
0 V Differential
V
ISO
V
ISO(min)
V
ISO(max)
V
SS
(16) t
AC
and t
DQSCK
depend on the clock jitter. These timing are measured at stable clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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