參數(shù)資料
型號: W9751G6JB-25A
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84
文件頁數(shù): 11/86頁
文件大?。?/td> 1030K
代理商: W9751G6JB-25A
W9751G6JB
Publication Release Date: Mar. 10, 2010
- 19 -
Revision A02
CMD
CLK
ODT
Rtt
Updating
New setting
tIS
tMOD,min
tMOD,max
tAOFD
EMRS
NOP
Old setting
1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
2) “setting” in this diagram is the Register and I/O setting, not what is measured from outside.
Figure 10—ODT update delay timing - tMOD
However, to prevent any impedance glitch on the channel, the following conditions must be met.
tAOFD must be met before issuing the EMRS command.
ODT must remain LOW for the entire duration of tMOD window, until tMOD,max is met.
Now the ODT is ready for normal operation with the new setting, and the ODT signal may be raised
again to turned on the ODT. Following timing diagram shows the proper Rtt update procedure.
CLK
CMD
ODT
Rtt
Old setting
New setting
tAOND
tIS
tMOD,max
tAOFD
EMRS
NOP
1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
2)“setting"in this diagram is what is measured from outside.
Figure 11—ODT update delay timing - tMOD, as measured from outside
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