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參數(shù)資料
| 型號： | W9751G6JB-25A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件頁數(shù)： | 46/86頁 |
| 文件大?。?/td> | 1030K |
| 代理商： | W9751G6JB-25A |
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W9751G6JB
Publication Release Date: Mar. 10, 2010
- 50 -
Revision A02
25. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667, DDR2-800.
Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Examples:
For DDR2-667/800: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
For DDR2-1066: tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+3, even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min.
26. These parameters are measured from a command/address signal (CKE, CS , RAS , CAS , WE , ODT, BA0, A0, A1, etc.)
transition edge to its respective clock signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
27. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can
be executed.
28. These parameters are measured from a data strobe signal ((L/U)DQS/ DQS ) crossing to its respective clock signal
(CLK/ CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as
these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
29. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective
data strobe signal ((L/U)DQS/ DQS ) crossing.
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PDF描述 |
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| W9751G8JB-18 | DDR DRAM, PBGA84 |
| W9812G21H-6I | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| W9812G6JH-6 | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| W986416AH-10 | 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
| W9751G6KB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6KB-18 | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9751G6KB-25 | 功能描述:IC DDR2 SDRAM 512MBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W9751G6KB25A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
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