參數(shù)資料
型號(hào)： W9751G6JB-25A
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84
文件頁數(shù)： 47/86頁
文件大小： 1030K
代理商： W9751G6JB-25A
W9751G6JB
Publication Release Date: Mar. 10, 2010
- 51 -
Revision A02
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
DDR2-667
DDR2-800
DDR2-1066
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
Clock period jitter
tJIT(per)
-125
125
-100
100
-90
90
pS
Clock period jitter during DLL locking period
tJIT(per,lck)
-100
100
-80
80
-80
80
pS
Cycle to cycle clock period
tJIT(cc)
-250
250
-200
200
-180
180
pS
Cycle to cycle clock period jitter during DLL
locking period
tJIT(cc,lck)
-200
200
-160
160
-160
160
pS
Cumulative error across 2 cycles
tERR(2per)
-175
175
-150
150
-132
132
pS
Cumulative error across 3 cycles
tERR(3per)
-225
225
-175
175
-157
157
pS
Cumulative error across 4 cycles
tERR(4per)
-250
250
-200
200
-175
175
pS
Cumulative error across 5 cycles
tERR(5per)
-250
250
-200
200
-188
188
pS
Cumulative error across n cycles,
n = 6 ... 10, inclusive
tERR(6-10per)
-350
350
-300
300
-250
250
pS
Cumulative error across n cycles,
n = 11 ... 50, inclusive
tERR(10-50per)
-450
450
-450
450
-425
425
pS
Duty cycle jitter
tJIT(duty)
-125
125
-100
100
-75
75
pS
Definitions:
- tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCK(avg) =
∑
=
N
j
tCK
1
/ N
where
N = 200
- tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tCH(avg) =
∑
=
N
j
tCH
1
/ (N × tCK(avg))
where
N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
tCL(avg) =
∑
=
N
j
tCL
1
/ (N × tCK(avg))
where
N = 200
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W9751G6JB-3 制造商:Winbond Electronics Corp 功能描述:512MB DDRII
W9751G6KB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
W9751G6KB-18 制造商:Winbond Electronics Corp 功能描述:IC MEMORY
W9751G6KB-25 功能描述:IC DDR2 SDRAM 512MBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6
W9751G6KB25A 制造商:WINBOND 制造商全稱:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle
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