參數(shù)資料
型號： W9751G6JB-25A
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84
文件頁數(shù)： 51/86頁
文件大?。?/td> 1030K
代理商： W9751G6JB-25A
W9751G6JB
Publication Release Date: Mar. 10, 2010
- 55 -
Revision A02
43. tIS and tIH (input setup and hold) derating.
tIS/tIH Derating values for DDR2-667, DDR2-800 and DDR2-1066
ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800 and DDR2-1066
CLK/ CLK Differential Slew Rate
2.0 V/nS
1.5 V/nS
1.0 V/nS
Command/
Address
Slew Rate
(V/nS)
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
Unit
4.0
+150
+94
+180
+124
+210
+154
pS
3.5
+143
+89
+173
+119
+203
+149
pS
3.0
+133
+83
+163
+113
+193
+143
pS
2.5
+120
+75
+150
+105
+180
+135
pS
2.0
+100
+45
+130
+75
+160
+105
pS
1.5
+67
+21
+97
+51
+127
+81
pS
1.0
0
+30
+60
pS
0.9
-5
-14
+25
+16
+55
+46
pS
0.8
-13
-31
+17
-1
+47
+29
pS
0.7
-22
-54
+8
-24
+38
+6
pS
0.6
-34
-83
-4
-53
+26
-23
pS
0.5
-60
-125
-30
-95
0
-65
pS
0.4
-100
-188
-70
-158
-40
-128
pS
0.3
-168
-292
-138
-262
-108
-232
pS
0.25
-200
-375
-170
-345
-140
-315
pS
0.2
-325
-500
-295
-470
-265
-440
pS
0.15
-517
-708
-487
-678
-457
-648
pS
0.1
-1000
-1125
-970
-1095
-940
-1065
pS
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and
tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF(dc) to AC region’, use nominal slew rate for derating value. See Figure 20 Illustration of nominal slew rate for tIS.
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to AC region’, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line
for tIS.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded ‘DC to VREF(dc) region’, use nominal slew rate for derating value. See Figure 22 Illustration of nominal slew rate for tIH.
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF(dc) region’, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of
tangent line for tIH.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the
derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
相關(guān)PDF資料
PDF描述
W9751G8JB-18 DDR DRAM, PBGA84
W9812G21H-6I 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
W9812G21H-6C 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86
W9812G6JH-6 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54
W986416AH-10 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W9751G6JB-3 制造商:Winbond Electronics Corp 功能描述:512MB DDRII
W9751G6KB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
W9751G6KB-18 制造商:Winbond Electronics Corp 功能描述:IC MEMORY
W9751G6KB-25 功能描述:IC DDR2 SDRAM 512MBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6
W9751G6KB25A 制造商:WINBOND 制造商全稱:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*