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參數(shù)資料
| 型號(hào)： | WEDPNF8M722V-1010BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | WEDPNF8M722V-1010BC |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M722V-XBX
PROGRAM OPERATION
NOTE:
NOTE: See Table 7 for program command sequence.
FIG. 6
WORD/BYTE PROGRAM COMMAND SEQUENCE
The system may program the devices by word or byte, de-
pending on the state of the BYTE1-2 pins. Programming is a
four-bus-cycle operation. The program command se-
quence is initiated by writing two unlock write cycles, fol-
lowed by the program set-up command. The program ad-
dress and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required
to provide further controls or timing. The device automati-
cally provides internally generated program pulses and veri-
fies the programmed cell margin. Table 7 shows the ad-
dress and data requirements for the byte program com-
mand sequence.
When the Embedded program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using FD7, FD6, or RY/BY1and
FD23, 22 or RY/BY2 respectively. See “Write Operation Sta-
tus” for information on these status bits.
Any commands written to the device during the Embed-
ded Program Algorithm are ignored. Note that a hardware
hardware
reset
reset immediately terminates the programming operation.
The program command sequences should be reinitiated
once the device has reset to reading array data, to ensure
date integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0”
A bit cannot be programmed from a “0”
back to a “1”.
back to a “1”. Attempting to do so may halt the operation
and set FD5 and FD21 respectively to “1”, or cause the Data
Polling algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is still
“0”. Only erase operations can convert a “0” to a “1”.
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| WEDPNF8M722V-1010BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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