參數(shù)資料
型號(hào)： WEDPNF8M722V-1010BC
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 7/43頁(yè)
文件大?。?/td> 1280K
代理商： WEDPNF8M722V-1010BC
15
1 5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M722V-XBX
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the in-
ternal command register. The command register itself does
not occupy any addressable memory location. The register
is composed of latches that store the commands, along
with the address and data information needed to execute
the command. The contents of the register serve as inputs
to the internal state machine. The state machine outputs
dictate the function of the device. Table 4 lists the device
bus operations, the inputs and control levels required, and
the resulting output. The following subsections describe
each of these operations in fur ther detail.
ming and erase operations. Reading data out of the device
is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. This initiates the Embedded Program al-
gorithm – an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin. The
Unlock Bypass mode faciclitates faster programming times
by requiring only two write cycles to program data instead
of four.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm –
an internal algorithm that automaticaally preprograms the
array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically times
the erase pulse widths and verifies proper cell margin.
The host system can detect whether as program or erase
operation is complete by observing the RY/BY1-2 pin, or by
reading FD
7/FD23 (Data Polling) and FD6/FD22 (toggle) status
bits. After a program or erase cycle has been completed,
the device is ready to read array data or accept another com-
mand.
The Sector Erase Architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectords. The device is fully erased when
shipped from the factory.
Hardware Data Protection measures include a low Vcc de-
tector that automatically inhibits write operations during
power transitions. The Hardware Sector Protection feature
disables bith program and erase operations in any combi-
nation of sectors of memory. This can be achieved in-sys-
tem or via programming equipment.
The Erase Suspend feature enables the user to put erase
on hold for any period of time to read data from, or pro-
gram data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The Hardware Reset (RST) pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RST pin may be tied to the reset circuitry. A
system reset would thus also reset the device, enabling the
system microprocessor to read the boot-up firmware from
Flash memory.
The device offers two power saving features. When ad-
dresses have been stable for specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes
WORD/BYTE CONFIGURATION
The BYTE1 pin controls whether the device data I/O pins
FD
O-15 operate in the byte or word configuration. If the BYTE1
pin is set at logic ‘1’, the device is in word configuration,
FD
0-15 are active and controlled by FCS1 and FOE.
If the BYTE1 pin is set at logic ‘0’, the device is in byte con-
figuration, and only data I/O pins FD
0-7 are active and con-
trolled by FCS
1 and FOE. The data I/O pins FD8-14 are tri stated,
and the FD
15 pin is used as an input for the LSB (FA-1) ad-
dress function.
The BYTE2 pin controls whether the device data I/O pins
FD
16-31 operate in the byte or word configuration. If the
BYTE2 pin is set at logic ‘1’, the device is in word configu-
ration, FD0-15 are active and controlled by FCS
2 and FOE.
If the BYTE2 pin is set at logic ‘0’, the device is in byte con-
figuration, and only data I/O pins FD
0-7 are active and con-
trolled by FCS
2 and FOE. The data I/O pins FD8-14 are tri stated,
and the FD
15 pin is used as an input for the LSB (FA-1) ad-
dress function.
To read array data from the outputs, the system must drive
the FCS
1-2 and FOE pins to VIL. FCS1-2 are the power con-
trols and select the devices. FOE is the output control and
gates array data to the output pins. FWE should remain at
VIH. The BYTE1-2 pins determine whether the device out-
puts array data in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
REQUIREMENTS FOR READING
ARRAY DATA
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參數(shù)描述
WEDPNF8M722V-1010BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1010BM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1012BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1012BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1012BM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
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