參數(shù)資料
型號: X28HT010W
廠商: INTERSIL CORP
元件分類: DRAM
英文描述: 5V, Byte Alterable EEPROM
中文描述: 128K X 8 EEPROM 5V, 200 ns, UUC
封裝: WAFER
文件頁數(shù): 12/20頁
文件大小: 444K
代理商: X28HT010W
12
FN8105.1
February 12, 2007
Read Cycle
NOTE:
4. t
LZ
min.,t
HZ
, t
OLZ
min., and t
OHZ
are periodically sampled and not 100% tested. t
HZ
max. and t
OHZ
max. are measured, with C
L
= 5pF, from the point
when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
t
CE
t
RC
Address
CE
OE
WE
Data Valid
t
OE
t
LZ
t
OLZ
t
OH
t
AA
t
HZ
t
OHZ
Data I/O
V
IH
HIGH Z
Data Valid
Write Cycle Limits
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
WC
(Note 5)
Write cycle time
10
ms
t
AS
Address setup time
0
ns
t
AH
Address hold time
50
ns
t
CS
Write setup time
0
ns
t
CH
Write hold time
0
ns
t
CW
CE pulse width
100
ns
t
OES
OE HIGH setup time
10
ns
t
OEH
OE HIGH hold time
10
ns
t
WP
WE pulse width
100
ns
t
WPH
WE HIGH recovery
100
ns
t
DV
Data valid
1
μs
t
DS
Data setup
50
ns
t
DH
Data hold
0
ns
t
DW
Delay to next write
10
μs
t
BLC
Byte load cycle
0.2
100
μs
X28C010, X28HT010
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