參數(shù)資料
型號(hào)： X9520B20IB
廠商： Intersil Corporation
英文描述： Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors
中文描述： 三氯酚，葡萄牙，2kbit EEPROM存儲(chǔ)器，雙電壓監(jiān)視器
文件頁(yè)數(shù)： 13/33頁(yè)
文件大小： 561K
代理商： X9520B20IB
13
FN8206.0
March 8, 2005
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides
the user with a mechanism for changing and reading
the status of various parameters of the X9520 (See
Figure 17).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when V1 /
Vcc is powered down, then powered back up. The vola-
tile bits however, will always power-up to a known logic
state “0” (irrespective of their value at power-down).
A detailed description of the function of each of the CON-
STAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9520 device. This bit must first be enabled before
ANY write operation (to DCPs, EEPROM memory array,
or the CONSTAT register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as the
CONSTAT register, is aborted and no ACKNOWLEDGE
is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis-
ter) or until the X9520 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 18).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9520. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 18).
—When the X9520 is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used
to:
—Inhibit a write operation from being performed to cer-
tain addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper
position”).
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1 and
BL0 bits written to the CONSTAT register. It is possible
to lock the regions of EEPROM memory shown in the
table below:
If the user attempts to perform a write operation on a pro-
tected region of EEPROM memory, the operation is
aborted without changing any data in the array.
Bit(s)
WEL
RWEL
V2OS
V3OS
BL1 - BL0
POR1 - POR0
Description
Write Enable Latch bit
Register Write Enable Latch bit
V2 Output Status flag
V3 Output Status flag
Sets the Block Lock partition
Sets the Power-on Reset time
POR1
WEL
POR0
CS5
CS6
CS7
CS4
CS3
CS2
CS1
CS0
V3OS
V2OS
BL0
BL1
RWEL
Figure 17. CONSTAT Register Format
NV
NV
NV
NV
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
BL1
0
0
1
1
BL0
0
1
0
1
Protected Addresses
(Size)
None (Default)
C0h - FFh
(64 bytes
)
80h - FFh
(128 bytes
)
00h - FFh
(256 bytes)
Partition of array
locked
None (Default)
Upper 1/4
Upper 1/2
All
X9520
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