參數(shù)資料
型號(hào)： XA-H3
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit highly integrated microcontroller
中文描述： 的CMOS 16位高度集成的微控制器
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 183K
代理商： XA-H3
Philips Semiconductors
Preliminary specification
XA-H3
CMOS 16-bit highly integrated microcontroller
1999 Sep 24
14
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write or
Read Only
UART3 Registers
UART3 Write Register 0
R/W
8
8C0h
Command register
00h
UART3 Write Register 1
R/W
8
8C2h
Tx/Rx Interrupt & data transfer mode
xx
UART3 Write Register 2
R/W
8
8C4h
Extended Features Control
xx
UART3 Write Register 3
R/W
8
8C6h
Receive Parameter and Control
00h
UART3 Write Register 4
R/W
8
8C8h
Tx/Rx miscellaneous parameters & mode
00h
UART3 Write Register 5
R/W
8
8CAh
Tx. parameter and control
00h
Reserved – do not write
8
8CCh
Reserved – do not write
00h
Reserved – do not write
8
8CEh
Reserved – do not write
xx
UART3 Write Register 8
R/W
8
8D0h
Transmit Data Buffer
xx
UART3 Write Register 9
R/W
8
8D2h
Master Interrupt control
xx
UART3 Write Register 10
R/W
8
8D4h
Miscellaneous Tx/Rx control register
00h
UART3 Write Register 11
R/W
8
8D6h
Clock Mode Control
xx
UART3 Write Register 12
R/W
8
8D8h
Lower Byte of Baud rate time constant
00h
UART3 Write Register 13
R/W
8
8DAh
Upper Byte of Baud rate time constant
00h
UART3 Write Register 14
R/W
8
8DCh
Miscellaneous Control bits
xx
UART3 Write Register 15
R/W
8
8DEh
External / Status interrupt control
f8h
Reserved – do not write
8
8E8h
Reserved – do not write
00h
Reserved – do not write
8
8EAh
Reserved – do not write
00h
UART3 Read Register 0
RO
8
8E0h
Tx/Rx buffer and external status
UART3 Read Register 1
RO
8
8E2h
Receive condition status
Reserved – do not write
8E4h
UART3 Read Register 3
RO
8
8E6h
Interrupt Pending Bits
Reserved – do not write
8
8ECh
Reserved – do not write
Reserved – do not write
8
8EEh
Reserved – do not write
UART3 Read Register 8
RO
8
8F0h
Receive Buffer
Reserved – do not write
8F2h
–
UART3 Read Register 10
RO
8
8F4h
Clock status
Reserved – do not write
8F6-8FEh
Rx DMA Registers
DMA Control Register Ch.0 Rx
R/W
8
100h
Control Register
00h
FIFO Control & Status Reg Ch.0 Rx
R/W
8
101h
Control & Status Register
00h
Segment Register Ch.0 Rx
R/W
8
102h
Points to 64 k data segment
00h
Buffer Base Register Ch.0 Rx
R/W
8
104h
Wrap Reload Value for A15 – A8, A7 – A0
reloaded to zero by hardware
Upper Bound (plus 1) on A15 – A0
00h
Buffer Bound Register Ch.0 Rx
R/W
16
106h
0000h
Address Pointer Reg Ch.0 Rx
R/W
16
108h
Current Address pointer A15 – A0
0000h
Byte Count Register Ch.0 Rx
R/W
16
10Ah
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
Control Register
0000h
Data FIFO Register Ch.0 Lo Rx
R/W
16
10Ch
00h
00h
00h
00h
00h
Data FIFO Register Ch.0 Hi Rx
R/W
16
10Eh
DMA Control Register Ch.1 Rx
R/W
8
110h
FIFO Control & Status Register Ch.1 Rx
R/W
8
111h
Control & Status Register
00h
Segment Register Ch. 1 Rx
R/W
8
112h
Points to 64 k data segment
00h
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