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參數(shù)資料
| 型號： | XC18V04PC44C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SER C-TEMP 3.3V 44-PLCC |
| 標準包裝： | 26 |
| 可編程類型： | 系統(tǒng)內可編程 |
| 存儲容量： | 4Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱： | 122-1274 XC18V04PC44C-ND |
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008
Product Specification
24
R
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
06/11/03
4.0
Major revision.
Discontinued XC18V256 density.
Eliminated industrial ordering combinations.
Extended commercial temperature range.
Added MultiPRO Desktop Tool support.
Made change in capacitance values "DC Characteristics Over Operating Conditions".
Added Note (3) to Table 1.
Other minor edits.
12/15/03
4.1
Added specification (4.7 k
Ω) for recommended pull-up resistor on OE/RESET pin to section Reset
Added paragraph to section Standby Mode, page 14, concerning use of a pull-up resistor and/or
buffer on the DONE pin.
04/05/04
5.0
Major revision.
Figure 2: Revised configuration bitstream lengths for most Virtex-II FPGAs.
Replaced previous Figure 8 with new Figure 9.
Replaced previous power-on text section with new Reset and Power-On Reset Activation,
Added specification table Supply Voltage Requirements for Power-On Reset and Power-Down,
Added Footnote (5) to:
Specification table AC Characteristics Over Operating Conditions When Cascading for
Specification table AC Characteristics Over Operating Conditions When Cascading for
Numerous copyedits and wording changes/clarifications throughout.
07/20/04
5.0.1
Table 2: Removed reference to XC2VP125 FPGA.
03/06/06
5.1
page 15. Refer to Xilinx Device Package User Guide for package soldering guidelines.
Added information to Table 5 regarding variable JTAG IDCODE revision field.
01/11/08
5.2
Updated document template.
Updated URLs.
Tied RDWR_B and CS_B to GND to ensure valid logic-level Low in FPGA SelectMAP mode in
Updated "Marking Information," page 22 for 20-pin packaging.
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