- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19901 > XC18V04PC44C (Xilinx Inc)IC PROM SER C-TEMP 3.3V 44-PLCC PDF資料下載
參數(shù)資料
| 型號： | XC18V04PC44C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SER C-TEMP 3.3V 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 4Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱： | 122-1274 XC18V04PC44C-ND |
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008
Product Specification
3
R
CEO
12
DATA OUT
Chip Enable Output (CEO) is connected to the
CE input of the next PROM in the chain. This
output is Low when CE is Low and OE/RESET
input is High, AND the internal address counter
has been incremented beyond its Terminal
Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
21
27
13
11
OUTPUT
ENABLE
GND
GND is the ground connection.
6, 18, 28 & 41
3, 12, 24 &
34
11
TMS
MODE
SELECT
The state of TMS on the rising edge of TCK
determines the state transitions at the Test
Access Port (TAP) controller. TMS has an
internal 50 k
Ω resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
511
5
TCK
CLOCK
This pin is the JTAG test clock. It sequences
the TAP controller and all the JTAG test and
programming electronics.
713
6
TDI
DATA IN
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50 k
Ω resistive pull-up to provide a
logic 1 to the device if the pin is not driven.
39
4
TDO
DATA OUT
This pin is the serial output for all JTAG
instruction and data registers. TDO has an
internal 50 k
Ω resistive pull-up to provide a
logic 1 to the system if the pin is not driven.
31
37
17
VCCINT
Positive 3.3V supply voltage for internal logic.
17, 35 & 38(3)
23, 41 &
44(3)
18 & 20(3)
VCCO
Positive 3.3V or 2.5V supply voltage connected
to the input buffers(2) and output voltage
drivers.
8, 16, 26 & 36 14, 22, 32 &
42
19
NC
No connects.
1, 2, 4,
11, 12, 20, 22,
23, 24, 30, 32,
33, 34, 37, 39,
44
1, 6, 7, 8,
10, 17, 18,
26, 28, 29,
30, 36, 38,
39, 40, 43
Notes:
1.
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF
→D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
2.
For devices with IDCODES 0502x093h, the input buffers are supplied by VCCINT.
3.
For devices with IDCODES 0503x093h, the following VCCINT pins are no-connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package, and pin 20 in 20-pin SOIC and 20-pin PLCC packages.
Table 1: Pin Names and Descriptions (Cont’d)
Pin
Name
Boundary-
Scan Order
Function
Pin Description
44-pin VQFP
44-pin
PLCC
20-pin
SOIC &
PLCC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGM22DTMH | CONN EDGECARD 44POS R/A .156 SLD |
| XC17V04PC44I | IC PROM SER 4MBIT 3.3V 44-PLCC |
| RSA36DRSZ-S664 | CONN EDGECARD 72POS DIP .125 SLD |
| XC17V04PC20I | IC PROM SER 4MBIT 3.3V 20-PLCC |
| T95R336M035EAAS | CAP TANT 33UF 35V 20% 2824 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC18V04-PC44C | 制造商:Xilinx 功能描述: |
| XC18V04PC44C0100 | 制造商:Xilinx 功能描述: |
| XC18V04PC44C0901 | 制造商:Xilinx 功能描述: |
| XC18V04PC44C0936 | 制造商:Xilinx 功能描述:XLXXC18V04PC44C0936 IC SYSTEM GATE |
| XC18V04PC44C1 | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。