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參數(shù)資料
| 型號(hào)： | XC2S100-5FG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 59/99頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V 600 CLB'S 256-FBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 600 |
| 邏輯元件/單元數(shù)： | 2700 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 176 |
| 門數(shù)： | 100000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-FBGA（17x17） |
| 其它名稱： | 122-1226 XC2S100-5FG256C-ND |
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Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
62
R
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of
the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark
timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were
determined through statistical measurement at the package
pins using a clock mirror configuration and matched drivers.
Figure 52, page 63, provides definitions for various
parameters in the table below.
Symbol
Description
Speed Grade
Units
-6
-5
Min
Max
Min
Max
FCLKINHF
Input clock frequency (CLKDLLHF)
60
200
60
180
MHz
FCLKINLF
Input clock frequency (CLKDLL)
25
100
25
90
MHz
TDLLPWHF
Input clock pulse width (CLKDLLHF)
2.0
-
2.4
-
ns
TDLLPWLF
Input clock pulse width (CLKDLL)
2.5
-
3.0
-
ns
Symbol
Description
F
CLKIN
CLKDLLHF
CLKDLL
Units
Min
Max
Min
Max
TIPTOL
Input clock period tolerance
-
1.0
-
1.0
ns
TIJITCC
Input clock jitter tolerance (cycle-to-cycle)
-
±150
-
±300
ps
TLOCK
Time required for DLL to acquire lock
> 60 MHz
-
20
-
20
μs
50-60 MHz
-
25
μs
40-50 MHz
-
50
μs
30-40 MHz
-
90
μs
25-30 MHz
-
120
μs
TOJITCC
Output jitter (cycle-to-cycle) for any DLL clock output(1)
-
±60
-
±60
ps
TPHIO
Phase offset between CLKIN and CLKO(2)
-
±100
-
±100
ps
TPHOO
Phase offset between clock outputs on the DLL(3)
-
±140
-
±140
ps
TPHIOM
Maximum phase difference between CLKIN and CLKO(4)
-
±160
-
±160
ps
TPHOOM
Maximum phase difference between clock outputs on the DLL(5)
-
±200
-
±200
ps
Notes:
1.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
3.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5.
Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
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相關(guān)代理商/技術(shù)參數(shù) |
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| XC2S1005-FG256C | 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 2700 Cell, 256 Pin, Plastic, BGA |
| XC2S1005FG256I | 制造商:XILINX 功能描述:New |
| XC2S100-5FG256I | 功能描述:IC FPGA 2.5V I-TEMP 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S1005FG456C | 制造商:Xilinx 功能描述: |
| XC2S100-5FG456C | 功能描述:IC FPGA 2.5V 600 CLB'S 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
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