參數(shù)資料
型號： XC2S200-5FGG456I
廠商： Xilinx Inc
文件頁數(shù)： 50/99頁
文件大小： 0K
描述： IC SPARTAN-II FPGA 200K 456-FBGA
標準包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計： 57344
輸入/輸出數(shù)： 284
門數(shù)： 200000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 456-BBGA
供應商設備封裝： 456-FBGA
其它名稱： 122-1313
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
54
R
Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and
junction temperature). Values apply to all Spartan-II devices
unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
CTT
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.4
VREF + 0.4
8
–8
AGP
–0.5
VREF – 0.2
VREF + 0.2
3.6
10% VCCO
90% VCCO
Note (2)
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2.
Tested according to the relevant specifications.
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
Symbol
Description
Device
Speed Grade
Units
All
-6
-5
Min
Max
TICKOFDLL
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, with DLL.
All
2.9
3.3
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables "Constants for Calculating TIOOP" and "Delay Measurement
3.
DLL output jitter is already included in the timing calculation.
4.
For data output with different standards, adjust delays with the values shown in "IOB Output Delay Adjustments for Different
Standards," page 59. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Symbol
Description
Device
Speed Grade
Units
All
-6
-5
Min
Max
TICKOF
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, without DLL.
XC2S15
4.5
5.4
ns
XC2S30
4.5
5.4
ns
XC2S50
4.5
5.4
ns
XC2S100
4.6
5.5
ns
XC2S150
4.6
5.5
ns
XC2S200
4.7
5.6
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables "Constants for Calculating TIOOP" and "Delay Measurement
3.
For data output with different standards, adjust delays with the values shown in "IOB Output Delay Adjustments for Different
Standards," page 59. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
相關(guān)PDF資料
PDF描述
AMC35DRXH CONN EDGECARD 70POS .100 DIP SLD
XC2S200-6FG456C IC FPGA 2.5V C-TEMP 456-FBGA
AMM25DTMI CONN EDGECARD 50POS R/A .156 SLD
3341-31BULK CONN JACKSOCKET M2.5/4-40 0.40"
XC2S200-5FG456I IC FPGA 2.5V I-TEMP 456-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S200-5PQ208C 功能描述:IC FPGA 2.5V 1176 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27）
XC2S200-5PQ208I 功能描述:IC FPGA 2.5V I-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27）
XC2S200-5PQ208Q 制造商:Xilinx 功能描述:XILINX XC2S200-5PQ208Q FPGA - Trays 制造商:Xilinx 功能描述:Xilinx XC2S200-5PQ208Q FPGA
XC2S200-5PQG208C 功能描述:IC SPARTAN-II FPGA 200K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27）
XC2S200-5PQG208I 功能描述:IC SPARTAN-II FPGA 200K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*