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參數資料
| 型號： | XC2S300E-6PQG208C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 22/108頁 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-IIE FPGA 300K 208PQFP |
| 產品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數： | 1536 |
| 邏輯元件/單元數： | 6912 |
| RAM 位總計： | 65536 |
| 輸入/輸出數： | 146 |
| 門數： | 300000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 122-1326 |
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20
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 15.
BSDL (Boundary Scan Description Language) files for
Spartan-IIE family devices are available on the Xilinx web
site.
Spartan-IIE FPGA boundary scan IDCODE values are
shown in Table 9.
Development System
Spartan-IIE FPGAs are supported by the Xilinx ISE CAE
tools. The basic methodology for Spartan-IIE FPGA design
consists of three interrelated steps: design entry, imple-
mentation, and verification. Industry-standard tools are
used for design entry and simulation, while Xilinx provides
proprietary architecture-specific tools for implementation.
The Xilinx development system is integrated under the
Xilinx Project Navigator software, providing designers with a
common user interface regardless of their choice of entry
and verification tools. The software simplifies the selection
of implementation options with pull-down menus and on-line
help.
Several advanced software features facilitate Spartan-IIE
FPGA design. CORE Generator tool functions, for exam-
ple, include macros with relative location constraints to
guide their placement. They help ensure optimal implemen-
tation of common functions.
For HDL design entry, the Xilinx FPGA development system
provides interfaces to several synthesis design environ-
ments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Spartan-IIE FPGAs are supported by a unified library of
standard functions. This library contains over 400 primitives
and macros, ranging from 2-input AND gates to 16-bit accu-
mulators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
The design environment supports hierarchical design entry,
with high-level designs that comprise major functional
blocks, while lower-level designs define the logic in these
blocks. These hierarchical design elements are automati-
cally combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
Figure 15: Boundary Scan Bit Sequence
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
(TDI end)
DS001_10_032300
Table 9: Spartan-IIE IDCODE Values
Device
IDCODE
Version
Family
Array Size
Manufacturer
Required
XC2S50E
XXXX
0000 101
0 0001 0000
0000 1001 001
1
XC2S100E
XXXX
0000 101
0 0001 0100
0000 1001 001
1
XC2S150E
XXXX
0000 101
0 0001 1000
0000 1001 001
1
XC2S200E
XXXX
0000 101
0 0001 1100
0000 1001 001
1
XC2S300E
XXXX
0000 101
0 0010 0000
0000 1001 001
1
XC2S400E
XXXX
0000 101
0 0010 1000
0000 1001 001
1
XC2S600E
XXXX
0000 101
0 0011 0000
0000 1001 001
1
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| GLC50-3.3G | PS SWITCHER 50W 3.3V 8.0A |
| XC2S300E-6PQ208C | IC FPGA 1.8V 1536 CLB'S 208-PQFP |
| KA7815AE | IC REG LDO 15V 1A TO-220 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S300E-6PQG208I | 功能描述:IC SPARTAN-IIE FPGA 300K 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-IIE 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC2S300E-6TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S300E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S300E-6TQG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S300E-6TQG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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