參數(shù)資料
型號(hào): XC2S300E-6PQG208C
廠商: Xilinx Inc
文件頁數(shù): 64/108頁
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 300K 208PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1536
邏輯元件/單元數(shù): 6912
RAM 位總計(jì): 65536
輸入/輸出數(shù): 146
門數(shù): 300000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1326
DS077-4 (v3.0) August 9, 2013
59
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O (DLL), L17P
4
P56
-
I/O
4
P57
-
I/O, VREF
Bank 4
4
P58
-
All
I/O, L16N_YY
4
P59
All
-
I/O, L16P_YY
4
P60
All
-
VCCINT
-
P61
-
GND
-
P62
-
I/O, L15N_YY
4
P63
All
-
I/O, L15P_YY
4
P64
All
XC2S100E
I/O
4
P65
-
I/O, VREF
Bank 4
4
P66
-
All
I/O
4
P67
-
I/O, L14N_YY
4
P68
All
-
I/O, L14P_YY
4
P69
All
-
GND
-
P70
-
DONE
3
P71
-
VCCO
-
P72
-
PROGRAM
-
P73
-
I/O (INIT),
L13N_YY
3
P74
All
-
I/O (D7),
L13P_YY
3
P75
All
-
I/O
3
P76
-
I/O, VREF
Bank 3
3
P77
-
All
I/O
3
P78
-
I/O, L12N
3
P79
XC2S50E
XC2S100E
I/O (D6), L12P
3
P80
XC2S50E
-
GND
-
P81
-
I/O (D5),
L11N_YY
3
P82
All
-
I/O, L11P_YY
3
P83
All
-
I/O
3
P84
-
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
I/O, VREF
Bank 3, L10N
3
P85
XC2S50E
All
I/O (D4), L10P
3
P86
XC2S50E
-
I/O
3
P87
-
VCCINT
-
P88
-
I/O (TRDY)
3
P89
-
VCCO
-
P90
-
GND
-
P91
-
I/O (IRDY)
2
P92
-
I/O
2
P93
-
I/O (D3), L9N
2
P94
XC2S50E
-
I/O, VREF
Bank 2, L9P
2
P95
XC2S50E
All
I/O
2
P96
-
I/O, L8N_YY
2
P97
All
-
I/O (D2),
L8P_YY
2
P98
All
-
GND
-
P99
-
I/O (D1), L7N
2
P100
XC2S50E
-
I/O, L7P
2
P101
XC2S50E
XC2S100E
I/O
2
P102
-
I/O, VREF
Bank 2
2
P103
-
All
I/O
2
P104
-
I/O (DIN, D0),
L6N_YY
2
P105
All
-
I/O (DOUT,
BUSY),
L6P_YY
2
P106
All
-
CCLK
2
P107
-
VCCO
-
P108
-
TDO
2
P109
-
GND
-
P110
-
TDI
-
P111
-
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
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