參數(shù)資料
型號(hào): XC2S300E-6PQG208C
廠商: Xilinx Inc
文件頁數(shù): 67/108頁
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 300K 208PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1536
邏輯元件/單元數(shù): 6912
RAM 位總計(jì): 65536
輸入/輸出數(shù): 146
門數(shù): 300000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1326
DS077-4 (v3.0) August 9, 2013
61
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
In the PQ208 package, all VCCO pins must be connected to
the same voltage.
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
GND
-
P1
-
TMS
-
P2
-
I/O
7
P3
-
I/O
7
P4
-
XC2S200E,
300E
I/O
7
P5
-
I/O, VREF
Bank 7,
L49P
7
P6
XC2S50E,
150E, 200E,
300E
All
I/O, L49N
7
P7
XC2S50E,
150E, 200E,
300E
-
I/O
7
P8
-
I/O
7
P9
-
I/O, L48P
7
P10
XC2S50E,
300E
XC2S100E,
150E, 200E,
300E
I/O, L48N
7
P11
XC2S50E,
300E
-
GND
-
P12
-
VCCO
-
P13
-
VCCINT
-
P14
-
I/O,
L47P_YY
7
P15
All
-
I/O,
L47N_YY
7
P16
All
-
I/O,
L46P_YY
7
P17
All
-
I/O,
L46N_YY
7
P18
All
-
GND
-
P19
-
I/O, VREF
Bank 7,
L45P
7
P20
XC2S50E,
300E
All
I/O, L45N
7
P21
XC2S50E,
300E
-
I/O
7
P22
-
I/O,
L44P_YY
7
P23
All
-
I/O (IRDY),
L44N_YY
7
P24
All
-
GND
-
P25
-
VCCO
-
P26
-
I/O (TRDY)
6
P27
-
VCCINT
-
P28
-
I/O
6
P29
-
I/O, L43P
6
P30
XC2S50E,
300E
-
I/O, VREF
Bank 6,
L43N
6
P31
XC2S50E,
300E
All
GND
-
P32
-
I/O,
L42P_YY
6
P33
All
-
I/O,
L42N_YY
6
P34
All
-
I/O,
L41P_YY
6
P35
All
-
I/O,
L41N_YY
6
P36
All
-
VCCINT
-
P37
-
VCCO
-
P38
-
GND
-
P39
-
I/O, L40P
6
P40
XC2S50E,
300E
-
I/O, L40N
6
P41
XC2S50E,
300E
XC2S100E,
150E, 200E,
300E
I/O
6
P42
-
I/O
6
P43
-
I/O
6
P44
-
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
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