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| 型號： | XC2S400E-6FG456I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XC2S400E-6FG456I |
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
DS077-3 (v2.0) November 18, 2002
Product Specification
www.xilinx.com
1-800-255-7778
13
R
DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
worst-case values across the recommended operating con-
ditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 1, page 14
, provides definitions for various parame-
ters in the table below.
Symbol
F
CLKINHF
F
CLKINLF
T
DLLPW
Description
F
CLKIN
-
-
≥
25 MHz
≥
50 MHz
≥
100 MHz
≥
150 MHz
≥
200 MHz
≥
250 MHz
≥
300 MHz
Speed Grade
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
-7
-6
Min
60
25
5.0
3.0
2.4
2.0
1.8
1.5
1.3
Max
320
160
-
-
-
-
-
-
-
Min
60
25
5.0
3.0
2.4
2.0
1.8
1.5
NA
Max
275
135
-
-
-
-
-
-
-
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width
Symbol
T
IPTOL
T
IJITCC
T
LOCK
Description
F
CLKIN
CLKDLLHF
Min
-
-
-
-
-
-
-
-
-
-
-
-
CLKDLL
Min
-
-
-
-
-
-
-
-
-
-
-
-
Units
ns
ps
μ
s
μ
s
μ
s
μ
s
μ
s
ps
ps
ps
ps
ps
Max
1.0
±150
20
-
-
-
-
±60
±100
±140
±160
±200
Max
1.0
±300
20
25
50
90
120
±60
±100
±140
±160
±200
Input clock period tolerance
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock
(1)
> 60 MHz
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
T
OJITCC
T
PHIO
T
PHOO
T
PHIOM
T
PHOOM
Notes:
1.
Commercial operating conditions. Add 30% for Industrial operating conditions.
2.
Output Jitter
is cycle-to-cycle jitter measured on the DLL output clock,
excluding
input clock jitter.
3.
Phase Offset between CLKIN and CLKO
is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding
output jitter and input clock jitter.
4.
Phase Offset between Clock Outputs on the DLL
is the worst-case fixed time difference between rising edges of any two DLL
outputs,
excluding
output jitter and input clock jitter.
5.
Maximum Phase Difference between CLKIN and CLKO
is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (
excluding
input clock jitter).
6.
Maximum Phase Difference between Clock Outputs on the DLL
is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (
excluding
input clock jitter).
Output jitter (cycle-to-cycle) for any DLL clock output
(2)
Phase offset between CLKIN and CLKO
(3)
Phase offset between clock outputs on the DLL
(4)
Phase difference between CLKIN and CLKO
(5)
Phase difference between clock outputs on the DLL
(6)
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| XC2S400E-6FGG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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