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參數(shù)資料
| 型號： | XC2S400E-6FG456I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XC2S400E-6FG456I |
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
6
www.xilinx.com
1-800-255-7778
DS077-3 (v2.0) November 18, 2002
Product Specification
R
Global Clock Setup and Hold for LVTTL Standard,
with
DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard,
without
DLL (Pin-to-Pin)
Symbol
Description
Speed Grade
Units
-7
-6
Min
Min
T
PSDLL
/ T
PHDLL
Input setup and hold time relative to global clock input signal
for LVTTL standard, no delay, IFF,
(1)
with
DLL
1.6 / 0
1.7 / 0
ns
Notes:
1.
2.
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DLL output jitter is already included in the timing calculation.
For data input with different standards, adjust the setup time delay by the values shown in
IOB Input Delay Adjustments for
Different Standards
, page 8
. For a global clock input with standards other than LVTTL, adjust delays with values from the
I/O
Standard Global Clock Input Adjustments
, page 12
.
A zero hold time listing indicates no hold time or a negative hold time.
3.
4.
5.
Symbol
Description
Device
Speed Grade
Units
-7
-6
Min
Min
T
PSFD
/ T
PHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,
(1)
without
DLL
XC2S50E
1.8 / 0
1.8 / 0
ns
XC2S100E
1.8 / 0
1.8 / 0
ns
XC2S150E
1.9 / 0
1.9 / 0
ns
XC2S200E
1.9 / 0
1.9 / 0
ns
XC2S300E
2.0 / 0
2.0 / 0
ns
XC2S400E
2.0 / 0
2.0 / 0
ns
XC2S600E
2.1 / 0
2.1 / 0
ns
Notes:
1.
2.
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
For data input with different standards, adjust the setup time delay by the values shown in
IOB Input Delay Adjustments for
Different Standards
, page 8
. For a global clock input with standards other than LVTTL, adjust delays with values from the
I/O
Standard Global Clock Input Adjustments
, page 12
.
3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S400E-6FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 676FBGA - Trays |
| XC2S400E-6FG676I | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 676FBGA - Trays |
| XC2S400E-6FGG456C | 功能描述:IC SPARTAN-IIE FPGA 400K 456FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2S400E-6FGG456I | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 456FBGA - Trays |
| XC2S400E-6FGG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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