參數(shù)資料
型號(hào)： XC2S400E-6FGG456C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 17/108頁(yè)
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 400K 456FBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-IIE
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計(jì)： 163840
輸入/輸出數(shù)： 329
門數(shù)： 400000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
其它名稱： 122-1327
16
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Table 7 shows the depth and width aspect ratios for the
block RAM.
The Spartan-IIE FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs. See Xilinx Application Note XAPP173 for
more information on block RAM.
Programmable Routing
It is the longest delay path that limits the speed of any
design. Consequently, the Spartan-IIE FPGA routing archi-
tecture and its place-and-route software were defined jointly
to minimize long-path delays and yield the best system per-
formance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
The software automatically uses the best available routing
based on user timing requirements. The details are pro-
vided here for reference.
Local Routing
The local routing resources, as shown in Figure 9, provide
the following three types of connections:
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM), described below.
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
General Purpose Routing
Most Spartan-IIE FPGA signals are routed on the general
purpose routing, and consequently, the majority of intercon-
nect resources are associated with this level of the routing
hierarchy. The general routing resources are located in hor-
izontal and vertical routing channels associated with the
rows and columns of CLBs. The general-purpose routing
resources are listed below.
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
I/O Routing
Spartan-IIE devices have additional routing resources
around their periphery that form an interface between the
CLB array and the IOBs. This additional routing, called the
VersaRing routing, facilitates pin-swapping and pin-lock-
ing, such that logic redesigns can adapt to existing PCB lay-
outs. Time-to-market is reduced, since PCBs and other
system components can be manufactured while the logic
design is still in progress.
Table 7: Block RAM Port Aspect Ratios
Width
Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0>
DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0>
DATA<15:0>
Figure 9: Spartan-IIE Local Routing
DS001_06_032300
CLB
GRM
To
Adjacent
GRM
To Adjacent
GRM
Direct
Connection
To Adjacent
CLB
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
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參數(shù)描述
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XC2S400E-6FGG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S400E-6FGG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S400E-6FT256C 功能描述:IC SPARTAN-IIE FPGA 400K 256FTBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC2S400E-6FT256I 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 256FTBGA - Trays
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