參數(shù)資料
型號(hào): XC2S400E-6FGG456C
廠商: Xilinx Inc
文件頁數(shù): 9/108頁
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 400K 456FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計(jì): 163840
輸入/輸出數(shù): 329
門數(shù): 400000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
其它名稱: 122-1327
106
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, L2N_YY
0
E5
All
-
I/O, L2N_YY
I/O, L1P_YY
0
B4
All
-
I/O, L1P_YY
I/O, L1N_YY
0
C4
All
-
I/O, L1N_YY
I/O, L0P
0
A3
XC2S600E
-
I/O
I/O, L0P_Y
I/O, L0N
0
B3
XC2S600E
-
I/O, L0N_Y
I/O
0
A4
-
I/O
TCK
-
A2
-
TCK
FG676 Differential Clock Pins
Clock
Bank
P Input
N Input
Pin
Name
Pin
Name
GCK0
4
AF14
GCK0, I
AE14
I/O (DLL), L126P
GCK1
5
AF13
GCK1, I
AE13
I/O (DLL), L126N
GCK2
1
A14
GCK2, I
B14
I/O (DLL), L23P
GCK3
0
A13
GCK3, I
B13
I/O (DLL), L23N
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
Additional FG676 Package Pins
VCCINT Pins
H8
H19
J9
J18
K10
K11
K16
K17
L10
L17
T10
T17
U10
U11
U16
U17
V9
V18
W8
W19
-
VCCO Bank 0 Pins
C5
C8
D11
J10
J11
K12
K13
VCCO Bank 1 Pins
C19
C22
D16
J16
J17
K14
K15
VCCO Bank 2 Pins
E24
H24
K18
L18
L23
M17
N17
VCCO Bank 3 Pins
P17
R17
T18
T23
U18
W24
AB24
VCCO Bank 4 Pins
U14
U15
V16
V17
AC16
AD19
AD22
VCCO Bank 5 Pins
U12
U13
V10
V11
AC11
AD5
AD8
VCCO Bank 6 Pins
P10
R10
T4
T9
U9
W3
AB3
VCCO Bank 7 Pins
H3
K9
L4
L9
M10
N10
E3
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