參數(shù)資料
型號(hào): XC2S400E-6FGG456C
廠商: Xilinx Inc
文件頁(yè)數(shù): 6/108頁(yè)
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 400K 456FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計(jì): 163840
輸入/輸出數(shù): 329
門數(shù): 400000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
其它名稱: 122-1327
DS077-4 (v3.0) August 9, 2013
103
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, L39N
1
F18
XC2S600E
-
I/O, L39N
I/O, L39N_Y
I/O, L38P
1
D18
XC2S600E
-
I/O, VREF Bank 1,
L38P_Y
I/O, L38N
1
C18
XC2S600E
-
I/O
I/O, L38N_Y
I/O, L37P_YY
1
B18
All
-
I/O, L37P_YY
I/O, L37N_YY
1
A18
All
-
I/O, L37N_YY
I/O, L36P_YY
1
H17
All
-
I/O, L36P_YY
I/O, L36N_YY
1
G17
All
-
I/O, L36N_YY
I/O, VREF Bank 1,
L35P_YY
1
E18
All
I/O, VREF Bank 1,
L35P_YY
I/O, VREF Bank 1,
L35P_YY
I/O, L35N_YY
1
E17
All
-
I/O, L35N_YY
I/O, L34P_YY
1
D17
All
-
I/O, L34P_YY
I/O, L34N_YY
1
C17
All
-
I/O, L34N_YY
I/O
1
H16
-
I/O
I/O, L33P
1
B17
XC2S600E
-
I/O, L33P
I/O, L33P_Y
I/O, L33N
1
A17
XC2S600E
-
I/O, L33N
I/O, L33N_Y
I/O
1
G16
-
I/O
I/O, L32P_YY
1
F16
All
-
I/O, L32P_YY
I/O, L32N_YY
1
E16
All
-
I/O, L32N_YY
I/O, L31P_YY
1
C16
All
-
I/O, L31P_YY
I/O, L31N_YY
1
B16
All
-
I/O, L31N_YY
I/O
1
A16
-
I/O
I/O, L30P
1
J15
-
I/O, L30P
I/O, L30N
1
H15
-
I/O, L30N
I/O
1
G15
-
I/O
I/O, L29P_YY
1
F15
All
-
I/O, L29P_YY
I/O, L29N_YY
1
E15
All
-
I/O, L29N_YY
I/O, VREF Bank 1,
L28P_YY
1
B15
All
I/O, VREF Bank 1,
L28P_YY
I/O, VREF Bank 1,
L28P_YY
I/O, L28N_YY
1
A15
All
-
I/O, L28N_YY
I/O
1
D15
-
I/O
I/O, L27P_YY
1
J14
All
-
I/O, L27P_YY
I/O, L27N_YY
1
H14
All
-
I/O, L27N_YY
I/O
1
G14
-
I/O
I/O, L26P
1
F14
XC2S600E
-
I/O, L26P
I/O, L26P_Y
I/O, L26N
1
E14
XC2S600E
-
I/O, L26N
I/O, L26N_Y
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
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