參數(shù)資料
型號(hào)： XC2S400E-6FGG456C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 29/108頁(yè)
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 400K 456FBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-IIE
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計(jì)： 163840
輸入/輸出數(shù)： 329
門數(shù)： 400000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
其它名稱： 122-1327
DS077-2 (v3.0) August 9, 2013
27
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simultane-
ously. To configure multiple devices in this way, wire the indi-
vidual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See Start-up,
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28 shows a flowchart of the write sequence
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
The timing for Slave Parallel mode is shown in Figure 26,
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1.
Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2.
On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3.
Repeat steps 1 and 2 until all the data has been sent.
4.
Deassert CS and WRITE.
Figure 20: Slave Parallel Configuration Circuit Diagram
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CCLK
DATA[7:0]
WRITE
BUSY
CS(0)
Spartan-IIE
DONE
INIT
PROGRAM
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CS(1)
Spartan-IIE
DS077-2_06_110102
GND
相關(guān)PDF資料
PDF描述
XA6SLX100-2FGG484I IC FPGA SPARTAN 6 484FGGBGA
25LC640T-E/SN IC EEPROM 64KBIT 2MHZ 8SOIC
SST25VF020B-80-4C-SAE-T IC FLASH SER 2MB 80MHZ SPI 8SOIC
XC6SLX100-N3FGG484I IC FPGA SPARTAN-6 484FPGA
SST25LF020A-33-4C-SAE IC FLASH SER 2MB 33HZ SPI 8SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S400E-6FGG456I 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 456FBGA - Trays
XC2S400E-6FGG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S400E-6FGG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S400E-6FT256C 功能描述:IC SPARTAN-IIE FPGA 400K 256FTBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC2S400E-6FT256I 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 256FTBGA - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*