參數(shù)資料
型號(hào): XC2S400E-6FGG456C
廠商: Xilinx Inc
文件頁數(shù): 7/108頁
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 400K 456FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計(jì): 163840
輸入/輸出數(shù): 329
門數(shù): 400000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
其它名稱: 122-1327
104
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, VREF Bank 1,
L25P
1
D14
XC2S600E
All
I/O, VREF Bank 1,
L25P
I/O, VREF Bank 1,
L25P_Y
I/O, L25N
1
C14
XC2S600E
-
I/O, L25N
I/O, L25N_Y
I/O
1
J13
-
I/O
I/O, L24P
1
C13
-
I/O, L24P
I/O, L24N
1
D13
-
I/O, L24N
I/O
1
H13
-
I/O
I/O (DLL), L23P
1
B14
-
I/O (DLL), L23P
GCK2, I
1
A14
-
GCK2, I
GCK3, I
0
A13
-
GCK3, I
I/O (DLL), L23N
0
B13
-
I/O (DLL), L23N
I/O
0
E13
-
I/O
I/O, L22P_YY
0
F13
All
-
I/O, L22P_YY
I/O, L22N_YY
0
G13
All
-
I/O, L22N_YY
I/O, L21P
0
A12
XC2S600E
-
I/O, L21P_Y
I/O, VREF Bank 0,
L21N
0
B12
XC2S600E
All
I/O, VREF Bank 0
I/O, VREF Bank 0,
L21N_Y
I/O, L20P
0
D12
XC2S600E
-
I/O, L20P
I/O, L20P_Y
I/O, L20N
0
E12
XC2S600E
-
I/O, L20N
I/O, L20N_Y
I/O
0
F12
-
I/O
I/O, L19P_YY
0
G12
All
-
I/O, L19P_YY
I/O, L19N_YY
0
H12
All
-
I/O, L19N_YY
I/O
0
J12
-
I/O
I/O, L18P_YY
0
A11
All
-
I/O, L18P_YY
I/O, VREF Bank 0,
L18N_YY
0
B11
All
I/O, VREF Bank 0,
L18N_YY
I/O, VREF Bank 0,
L18N_YY
I/O, L17P_YY
0
E11
All
-
I/O, L17P_YY
I/O, L17N_YY
0
F11
All
-
I/O, L17N_YY
I/O
0
C11
-
I/O
I/O, L16P
0
G11
-
I/O, L16P
I/O, L16N
0
H11
-
I/O, L16N
I/O
0
C10
-
I/O
I/O, L15P_YY
0
A10
All
-
I/O, L15P_YY
I/O, L15N_YY
0
B10
All
-
I/O, L15N_YY
I/O, L14P_YY
0
D10
All
-
I/O, L14P_YY
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
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