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參數(shù)資料
| 型號(hào)： | XC3S200-4VQG100I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 12/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3 FPGA 200K STD 100VQFP |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 480 |
| 邏輯元件/單元數(shù)： | 4320 |
| RAM 位總計(jì)： | 221184 |
| 輸入/輸出數(shù)： | 63 |
| 門數(shù)： | 200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
| 其它名稱： | 122-1712 XC3S200-4VQG100I-ND |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
109
Table 70: Spartan-3 FPGA Pin Definitions
Pin Name
Direction
Description
I/O: General-purpose I/O pins
I/O
User-defined as input, output,
bidirectional, three-state output,
open-drain output, open-source
output
User I/O:
Unrestricted single-ended user-I/O pin. Supports all I/O standards except
the differential standards.
I/O_Lxxy_#
User-defined as input, output,
bidirectional, three-state output,
open-drain output, open-source
output
User I/O, Half of Differential Pair:
Unrestricted single-ended user-I/O pin or half of a differential pair.
Supports all I/O standards including the differential standards.
DUAL: Dual-purpose configuration pins
IO_Lxxy_#/DIN/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7
Input during configuration
Possible bidirectional I/O after
configuration if SelectMap port is
retained
Otherwise, user I/O after
configuration
Configuration Data Port:
In Parallel (SelectMAP) modes, D0-D7 are byte-wide configuration data
pins. These pins become user I/Os after configuration unless the
SelectMAP port is retained via the Persist bitstream option.
In Serial modes, DIN (D0) serves as the single configuration data input.
This pin becomes a user I/O after configuration unless retained by the
Persist bitstream option.
IO_Lxxy_#/CS_B
Input during Parallel mode
configuration
Possible input after configuration
if SelectMap port is retained
Otherwise, user I/O after
configuration
Chip Select for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Chip Select signal.
This pin becomes a user I/O after configuration unless the SelectMAP port
is retained via the Persist bitstream option.
IO_Lxxy_#/RDWR_B
Input during Parallel mode
configuration
Possible input after configuration
if SelectMap port is retained
Otherwise, user I/O after
configuration
Read/Write Control for Parallel Mode Configuration:
In Parallel (SelectMAP) modes, this is the active-Low Write Enable,
active-High Read Enable signal. This pin becomes a user I/O after
configuration unless the SelectMAP port is retained via the Persist
bitstream option.
IO_Lxxy_#/
BUSY/DOUT
Output during configuration
Possible output after
configuration if SelectMap port is
retained
Otherwise, user I/O after
configuration
Configuration Data Rate Control for Parallel Mode, Serial Data
Output for Serial Mode:
In Parallel (SelectMAP) modes, BUSY throttles the rate at which
configuration data is loaded. This pin becomes a user I/O after
configuration unless the SelectMAP port is retained via the Persist
bitstream option.
In Serial modes, DOUT provides preamble and configuration data to
downstream devices in a multi-FPGA daisy-chain. This pin becomes a
user I/O after configuration.
IO_Lxxy_#/INIT_B
Bidirectional (open-drain) during
configuration
User I/O after configuration
Initializing Configuration Memory/Detected Configuration Error:
When Low, this pin indicates that configuration memory is being cleared.
When held Low, this pin delays the start of configuration. After this pin is
released or configuration memory is cleared, the pin goes High. During
configuration, a Low on this output indicates that a configuration data error
occurred. This pin always has an internal pull-up resistor to VCCO_4 or
VCCO_BOTTOM during configuration, regardless of the HSWAP_EN pin.
This pin becomes a user I/O after configuration.
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/VRN_# or
IO/VRN_#
Input when using DCI
Otherwise, same as I/O
DCI Reference Resistor for NMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is connected
between this pin and the VCCO supply for this bank. Otherwise, this pin is
a user I/O.
IO_Lxxy_#/VRP_# or
IO/VRP_#
Input when using DCI
Otherwise, same as I/O
DCI Reference Resistor for PMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is connected
between this pin and the ground supply. Otherwise, this pin is a user I/O.
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