參數(shù)資料
型號(hào)： XC3S200-4VQG100I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 7/272頁(yè)
文件大小： 0K
描述： SPARTAN-3 FPGA 200K STD 100VQFP
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3
LAB/CLB數(shù)： 480
邏輯元件/單元數(shù)： 4320
RAM 位總計(jì)： 221184
輸入/輸出數(shù)： 63
門數(shù)： 200000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
其它名稱： 122-1712
XC3S200-4VQG100I-ND
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Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
Product Specification
104
Revision History
Date
Version
Description
04/11/2003
1.0
Initial Xilinx release.
07/11/2003
1.1
Extended Absolute Maximum Rating for junction temperature in Table 28. Added numbers for typical
quiescent supply current (Table 34) and DLL timing.
02/06/2004
1.2
Revised VIN maximum rating (Table 28). Added power-on requirements (Table 30), leakage current
number (Table 33), and differential output voltage levels (Table 38) for Rev. 0. Published new quiescent
current numbers (Table 34). Updated pull-up and pull-down resistor strengths (Table 33). Added
LVDCI_DV2 and LVPECL standards (Table 37 and Table 38). Changed CCLK setup time (Table 66 and
03/04/2004
1.3
Added timing numbers from v1.29 speed files as well as DCM timing (Table 58 through Table 63).
08/24/2004
1.4
Added reference to errata documents on page 49. Clarified Absolute Maximum Ratings and added ESD
information (Table 28). Explained VCCO ramp time measurement (Table 30). Clarified IL specification
(Table 33). Updated quiescent current numbers and added information on power-on and surplus current
(Table 34). Adjusted VREF range for HSTL_III and HSTL_I_18 and changed VIH min for LVCMOS12
(Table 35). Added note limiting VTT range for SSTL2_II signal standards (Table 36). Calculated VOH and
VOL levels for differential standards (Table 38). Updated Switching Characteristics with speed file v1.32
(Table 40 through Table 48 and Table 51 through Table 56). Corrected IOB test conditions (Table 41).
Updated DCM timing with latest characterization data (Table 58 through Table 62). Improved DCM CLKIN
pulse width specification (Table 58). Recommended use of Virtex-II FPGA Jitter calculator (Table 61).
Improved DCM PSCLK pulse width specification (Table 62). Changed Phase Shifter lock time parameter
(Table 63). Because the BitGen option Centered_x#_y# is not necessary for Variable Phase Shift mode,
removed BitGen command table and referring text. Adjusted maximum CCLK frequency for the slave
serial and parallel configuration modes (Table 66). Inverted CCLK waveform (Figure 37). Adjusted JTAG
setup times (Table 68).
12/17/2004
1.5
Updated timing parameters to match v1.35 speed file. Improved VCCO ramp time specification (Table 30).
Added a note limiting the rate of change of VCCAUX (Table 32). Added typical quiescent current values for
the XC3S2000, XC3S4000, and XC3S5000 (Table 34). Increased IOH and IOL for SSTL2-I and SSTL2-II
standards (Table 36). Added SSO guidelines for the VQ, TQ, and PQ packages as well as edited SSO
guidelines for the FT and FG packages (Table 50). Added maximum CCLK frequencies for configuration
using compressed bitstreams (Table 66 and Table 67). Added specifications for the HSLVDCI standards
08/19/2005
1.6
Updated timing parameters to match v1.37 speed file. All Spartan-3 FPGA part types, except XC3S5000,
promoted to Production status. Removed VCCO ramp rate restriction from all mask revision ‘E’ and later
devices (Table 30). Added equivalent resistance values for internal pull-up and pull-down resistors
(Table 33). Added worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000 (Table 34).
Added industrial temperature range specification and improved typical quiescent current values
(Table 34). Improved the DLL minimum clock input frequency specification from 24 MHz down to 18 MHz
(Table 58). Improved the DFS minimum and maximum clock output frequency specifications (Table 60,
Table 61). Added new miscellaneous DCM specifications (Table 64), primarily affecting Industrial
temperature range applications. Updated Simultaneously Switching Output Guidelines and Table 50 for
QFP packages. Added information on SSTL18_II I/O standard and timing to support DDR2 SDRAM
interfaces. Added differential (or complementary single-ended) DIFF_HSTL_II_18 and DIFF_SSTL2_II
I/O standards, including DCI terminated versions. Added electro-static discharge (ESD) data for the
XC3S2000 and larger FPGAs (Table 28). Added link to Spartan-3 FPGA errata notices and how to
receive automatic notifications of data sheet or errata changes.
04/03/2006
2.0
Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in Table 39.
Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic
and I/O paths. Corrected labels for RPU and RPD and updated RPD conditions for in Table 33. Added final
mask revision ‘E’ specifications for LVDS_25, RSDS_25, LVDSEXT_25 differential outputs to Table 38.
Added BLVDS termination requirements to Figure 34. Improved recommended Simultaneous Switching
Outputs (SSOs) limits in Table 50 for quad-flat packaged based on silicon testing using devices soldered
on a printed circuit board. Updated Note 2 in Table 63. Updated Note 6 in Table 30. Added INIT_B
minimum pulse width specification, TINIT, to Table 65.
04/26/2006
2.1
Updated document links.
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