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參數(shù)資料
| 型號(hào)： | XC3S5000-4FGG900C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 198/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 5M STD 900-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 8320 |
| 邏輯元件/單元數(shù)： | 74880 |
| RAM 位總計(jì)： | 1916928 |
| 輸入/輸出數(shù)： | 633 |
| 門數(shù)： | 5000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應(yīng)商設(shè)備封裝： | 900-FBGA |
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Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
31
Digital Clock Manager (DCM)
Spartan-3 devices provide flexible, complete control over clock frequency, phase shift and skew through the use of the DCM
feature. To accomplish this, the DCM employs a Delay-Locked Loop (DLL), a fully digital control system that uses feedback
to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature
and voltage. This section provides a fundamental description of the DCM. For further information, refer to the chapter
entitled “Using Digital Clock Managers” in UG331.
Each member of the Spartan-3 family has four DCMs, except the smallest, the XC3S50, which has two DCMs. The DCMs
are located at the ends of the outermost Block RAM column(s). See Figure 1, page 3. The Digital Clock Manager is placed
in a design as the “DCM” primitive.
The DCM supports three major functions:
Clock-skew Elimination: Clock skew describes the extent to which clock signals may, under normal circumstances,
deviate from zero-phase alignment. It occurs when slight differences in path delays cause the clock signal to arrive at
different points on the die at different times. This clock skew can increase set-up and hold time requirements as well as
clock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. The
DCM eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that
is fed back. As a result, the two clock signals establish a zero-phase relationship. This effectively cancels out clock
distribution delays that may lie in the signal path leading from the clock output of the DCM to its feedback input.
Frequency Synthesis: Provided with an input clock signal, the DCM can generate a wide range of different output
clock frequencies. This is accomplished by either multiplying and/or dividing the frequency of the input clock signal by
any of several different factors.
X-Ref Target - Figure 18
Figure 18: Embedded Multiplier Primitives
Table 15: Embedded Multiplier Primitives Descriptions
Signal
Name
Direction
Function
A[17:0]
Input
Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the
enabled rising edge of CLK.
B[17:0]
Input
Apply the other 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before
the enabled rising edge of CLK.
P[35:0]
Output
The output on the P bus is a 36-bit product of the multiplicands A and B. In the case of the MULT18X18S
primitive, an enabled rising CLK edge updates the P bus.
CLK
Input(1)
CLK is only an input to the MULT18X18S primitive. The clock signal applied to this input, when enabled by
CE, updates the output register that drives the P bus.
CE
Input(1)
CE is only an input to the MULT18X18S primitive. Enable for the CLK signal. Asserting this input enables the
CLK signal to update the P bus.
RST
Input(1)
RST is only an input to the MULT18X18S primitive. Asserting this input resets the output register on an
enabled, rising CLK edge, forcing the P bus to all zeroes.
Notes:
1.
The control signals CLK, CE and RST have the option of inverted polarity.
DS099-2_17_091510
(a) Asynchronous 18-bit Multiplier
(b) 18-bit Multiplier with Register
A[17:0]
B[17:0]
P[35:0]
MULT18X18
A[17:0]
B[17:0]
CLK
CE
RST
P[35:0]
MULT18X18S
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| XC3S5000-4FGG900I | 功能描述:SPARTAN-3A FPGA 5M STD 900-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC3S5000-5FG1156C | 制造商:Xilinx 功能描述: |
| XC3S5000-5FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 5M GATES 74880 CELLS 725MHZ 1.2V 676FBGA - Trays |
| XC3S5000-5FG900C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 5M GATES 74880 CELLS 725MHZ 1.2V 900FBGA - Trays |
| XC3S5000-5FG900CES | 制造商:Xilinx 功能描述: |
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