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參數(shù)資料
| 型號： | XC3S5000-4FGG900C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 223/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 5M STD 900-FBGA |
| 產品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 27 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 8320 |
| 邏輯元件/單元數(shù)： | 74880 |
| RAM 位總計： | 1916928 |
| 輸入/輸出數(shù)： | 633 |
| 門數(shù)： | 5000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應商設備封裝： | 900-FBGA |
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Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
54
Additional Configuration Details
Additional details about the Spartan-3 FPGA configuration architecture and command set are available in UG332: Spartan-3
Generation Configuration User Guide and in application note XAPP452: Spartan-3 Advanced Configuration Architecture.
Powering Spartan-3 FPGAs
Voltage Regulators
Various power supply manufacturers offer complete power solutions for Xilinx FPGAs, including some with integrated
multi-rail regulators specifically designed for Spartan-3 FPGAs. The Xilinx Power Corner web page provides links to vendor
solution guides as well as Xilinx power estimation and analysis tools.
Power Distribution System (PDS) Design and Bypass/Decoupling Capacitors
Good power distribution system (PDS) design is important for all FPGA designs, especially for high-performance
applications. Proper design results in better overall performance, lower clock and DCM jitter, and a generally more robust
system. Before designing the printed circuit board (PCB) for the FPGA design, review application note XAPP623: Power
Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors.
Power-On Behavior
Spartan-3 FPGAs have a built-in Power-On Reset (POR) circuit that monitors the three power rails required to successfully
configure the FPGA. At power-up, the POR circuit holds the FPGA in a reset state until the VCCINT, VCCAUX, and VCCO Bank
4 supplies reach their respective input threshold levels (see Table 29, page 59). After all three supplies reach their respective
threshold, the POR reset is released and the FPGA begins its configuration process.
Because the three supply inputs must be valid to release the POR reset and can be supplied in any order, there are no
specific voltage sequencing requirements. However, applying the FPGA’s VCCAUX supply before the VCCINT supply uses the
least ICCINT current.
Once all three supplies are valid, the minimum current required to power-on the FPGA is equal to the worst-case quiescent
current, as specified in Table 34, page 62. Spartan-3 FPGAs do not require Power-On Surge (POS) current to successfully
configure.
Surplus ICCINT if VCCINT Applied before VCCAUX
If the VCCINT supply is applied before the VCCAUX supply, the FPGA may draw a surplus ICCINT current in addition to the
ICCINT quiescent current levels specified in Table 34. The momentary additional ICCINT surplus current might be a few
hundred milliamperes under nominal conditions, significantly less than the instantaneous current consumed by the bypass
capacitors at power-on. However, the surplus current immediately disappears when the VCCAUX supply is applied, and, in
response, the FPGA’s ICCINT quiescent current demand drops to the levels specified in Table 34. The FPGA does not use
nor does it require the surplus current to successfully power-on and configure. If applying VCCINT- before VCCAUX, ensure
that the regulator does not have a foldback feature that could inadvertently shut down in the presence of the surplus current.
Maximum Allowed VCCINT Ramp Rate on Early Devices, if VVCCINTSupply is Last in Sequence
All devices with a mask revision code ‘E’ or later do not have a VCCINT ramp rate requirement. See Mask and Fab Revisions,
Early Spartan-3 FPGAs were produced at a 200 mm wafer production facility and are identified by a fabrication/process
code of "FQ" on the device top marking, as shown in Package Marking, page 5. These "FQ" devices have a maximum
VCCINT ramp rate requirement if and only if VCCINT is the last supply to ramp, after the VCCAUX and VCCO Bank 4 supplies.
Minimum Allowed VCCO Ramp Rate on Early Devices
Devices shipped since 2006 essentially have no VCCO ramp rate limits, shown in Table 30, page 60. Similarly, all devices
with a mask revision code ‘E’ or later do not have a VCCO ramp rate limit. See Mask and Fab Revisions, page 58.
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| XC3S5000-4FGG900I | 功能描述:SPARTAN-3A FPGA 5M STD 900-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC3S5000-5FG1156C | 制造商:Xilinx 功能描述: |
| XC3S5000-5FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 5M GATES 74880 CELLS 725MHZ 1.2V 676FBGA - Trays |
| XC3S5000-5FG900C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 5M GATES 74880 CELLS 725MHZ 1.2V 900FBGA - Trays |
| XC3S5000-5FG900CES | 制造商:Xilinx 功能描述: |
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