參數(shù)資料
型號(hào)： XC3S500E-4FG320I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 154/227頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3E 320FBGA
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3E
LAB/CLB數(shù)： 1164
邏輯元件/單元數(shù)： 10476
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 232
門數(shù)： 500000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 320-BGA
供應(yīng)商設(shè)備封裝： 320-FBGA（19x19）
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
32
Initialization
The CLB storage elements are initialized at power-up,
during configuration, by the global GSR signal, and by the
individual SR or REV inputs to the CLB. The storage
elements can also be re-initialized using the GSR input on
the STARTUP_SPARTAN3E primitive. See Global Controls
Distributed RAM
For additional information, refer to the “Using Look-Up
Tables as Distributed RAM” chapter in UG331.
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One SLICEM
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or
G[4:1] become the address lines labeled A[4:1] in the
device model and A[3:0] in the design components,
providing a 16x1 configuration in one LUT. Multiple SLICEM
LUTs can be combined in various ways to store larger
amounts of data, including 16x4, 32x2, or 64x1
configurations in one CLB. The fifth and sixth address lines
required for the 32-deep and 64-deep configurations,
respectively, are implemented using the BX and BY inputs,
which connect to the write enable logic for writing and the
F5MUX and F6MUX for reading.
Writing to distributed RAM is always synchronous to the
SLICEM clock (WCLK for distributed RAM) and enabled by
the SLICEM SR input which functions as the active-High
Write Enable (WE). The read operation is asynchronous,
and, therefore, during a write, the output initially reflects the
old data at the address being written.
The distributed RAM outputs can be captured using the
flip-flops within the SLICEM element. The WE write-enable
control for the RAM and the CE clock-enable control for the
flip-flop are independent, but the WCLK and CLK clock
inputs are shared. Because the RAM read operation is
asynchronous, the output data always reflects the currently
addressed RAM location.
A dual-port option combines two LUTs so that memory
access is possible from two independent data lines. The
same data is written to both 16x1 memories but they have
independent read address lines and outputs. The dual-port
function is implemented by cascading the G-LUT address
lines, which are used for both read and write, to the F-LUT
write address lines (WF[4:1] in Figure 15), and by
cascading the G-LUT data input D1 through the DIF_MUX
in Figure 15 and to the D1 input on the F-LUT. One CLB
provides a 16x1 dual-port memory as shown in Figure 26.
Any write operation on the D input and any read operation
on the SPO output can occur simultaneously with and
independently from a read operation on the second
read-only port, DPO.
Table 17: Slice Storage Element Initialization
Signal
Description
SR
Set/Reset input. Forces the storage element into the
state specified by the attribute SRHIGH or SRLOW.
SRHIGH forces a logic 1 when SR is asserted.
SRLOW forces a logic 0. For each slice, set and reset
can be set to be synchronous or asynchronous.
REV
Reverse of Set/Reset input. A second input (BY)
forces the storage element into the opposite state.
The reset condition is predominant over the set
condition if both are active. Same
synchronous/asynchronous setting as for SR.
GSR
Global Set/Reset. GSR defaults to active High but can
be inverted by adding an inverter in front of the GSR
input of the STARTUP_SPARTAN3E element. The
initial state after configuration or GSR is defined by a
separate INIT0 and INIT1 attribute. By default, setting
the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
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XC3S500E-4FGG320C 功能描述:IC SPARTAN-3E FPGA 500K 320FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S500E-4FGG320I 功能描述:IC FPGA SPARTAN-3E 500K 320-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S500E-4FT256C 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 572MHZ 90NM 1.2V 256F - Trays
XC3S500E-4FT256I 功能描述:IC FPGA SPARTAN 3E 256FTBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S500E-4FT256I4003 制造商:Xilinx 功能描述:
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