參數(shù)資料
型號(hào): XC3S500E-4FG320I
廠商: Xilinx Inc
文件頁(yè)數(shù): 90/227頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3E 320FBGA
標(biāo)準(zhǔn)包裝: 84
系列: Spartan®-3E
LAB/CLB數(shù): 1164
邏輯元件/單元數(shù): 10476
RAM 位總計(jì): 368640
輸入/輸出數(shù): 232
門數(shù): 500000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 320-BGA
供應(yīng)商設(shè)備封裝: 320-FBGA(19x19)
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
18
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O or Input-only pin to a determined state.
Pull-up and pull-down resistors are commonly applied to
unused I/Os, inputs, and three-state outputs, but can be
used on any I/O or Input-only pin. The pull-up resistor
connects an IOB to VCCO through a resistor. The resistance
value depends on the VCCO voltage (see Module 3, DC and
Switching Characteristics for the specifications). The
pull-down resistor similarly connects an IOB to ground with
a resistor. The PULLUP and PULLDOWN attributes and
library primitives turn on these optional resistors.
By default, PULLDOWN resistors terminate all unused I/O
and Input-only pins. Unused I/O and Input-only pins can
alternatively be set to PULLUP or FLOAT. To change the
unused I/O Pad setting, set the Bitstream Generator
(BitGen) option UnusedPin to PULLUP, PULLDOWN, or
FLOAT. The UnusedPin option is accessed through the
Properties for Generate Programming File in ISE. See
During configuration a Low logic level on the HSWAP pin
activates pull-up resistors on all I/O and Input-only pins not
actively used in the selected configuration mode.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 12) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 8.
To adjust the drive strength for each output, the DRIVE
attribute is set to the desired drive strength: 2, 4, 6, 8, 12,
and 16. Unless otherwise specified in the FPGA application,
the software default IOSTANDARD is LVCMOS25, SLOW
slew rate, and 12 mA output drive.
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
X-Ref Target - Figure 11
Figure 11: Differential Inputs and Outputs
100
Ω
~120
Ω
Spartan-3E
Differential Input
Z0 = 50Ω
Spartan-3E
Differential
Output
Spartan-3E
Differential Input
with On-Chip
Differential
Terminator
Z0 = 50Ω
Spartan-3E
Differential
Output
DS312-2_24_082605
X-Ref Target - Figure 12
Figure 12: Keeper Circuit
Table 8: Programmable Output Drive Current
IOSTANDARD
Output Drive Current (mA)
2
4
6
8
12
16
LVTTL
LVCMOS33
LVCMOS25
-
LVCMOS18
-
LVCMOS15
-
LVCMOS12
-
Pull-up
Pull-down
Input Path
Output Path
Keeper
DS312-2_25_020807
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