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參數(shù)資料
| 型號(hào)： | XC3S500E-5FGG320C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 15/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 500K 320-FBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 1164 |
| 邏輯元件/單元數(shù)： | 10476 |
| RAM 位總計(jì)： | 368640 |
| 輸入/輸出數(shù)： | 232 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 320-BGA |
| 供應(yīng)商設(shè)備封裝： | 320-FBGA（19x19） |
| 配用： | 122-1536-ND - KIT STARTER SPARTAN-3E |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
111
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The Xilinx Power Corner website
provides links to vendor solution guides and Xilinx power
estimation and analysis tools.
Power Distribution System (PDS) Design
and Decoupling/Bypass Capacitors
review XAPP623: Power Distribution System (PDS) Design:
Using Bypass/Decoupling Capacitors.
Power-On Behavior
For additional power-on behavior information, including I/O
behavior before and during configuration, refer to the
“Sequence of Events” chapter in UG332.
Spartan-3E FPGAs have a built-in Power-On Reset (POR)
circuit that monitors the three power rails required to
successfully configure the FPGA. At power-up, the POR
circuit holds the FPGA in a reset state until the VCCINT,
VCCAUX, and VCCO Bank 2 supplies reach their respective
input threshold levels (see Table 74 in Module 3). After all
three supplies reach their respective thresholds, the POR
reset is released and the FPGA begins its configuration
process.
Supply Sequencing
Because the three FPGA supply inputs must be valid to
release the POR reset and can be supplied in any order,
there are no FPGA-specific voltage sequencing
requirements. Applying the FPGA’s VCCAUX supply before
the VCCINT supply uses the least ICCINT current.
Although the FPGA has no specific voltage sequence
requirements, be sure to consider any potential sequencing
requirement of the configuration device attached to the
FPGA, such as an SPI serial Flash PROM, a parallel NOR
Flash PROM, or a microcontroller. For example, Flash
PROMs have a minimum time requirement before the
PROM can be selected and this must be considered if the
3.3V supply is the last in the sequence. See Power-On
details.
When all three supplies are valid, the minimum current
required to power-on the FPGA equals the worst-case
quiescent current, specified in Table 79. Spartan-3E FPGAs
do not require Power-On Surge (POS) current to
successfully configure.
Surplus ICCINT if VCCINT Applied before VCCAUX
If the VCCINT supply is applied before the VCCAUX supply,
the FPGA might draw a surplus ICCINT current in addition to
might be a few hundred milliamperes under nominal
conditions, significantly less than the instantaneous current
consumed by the bypass capacitors at power-on. However,
the surplus current immediately disappears when the
VCCAUX supply is applied, and, in response, the FPGA’s
ICCINT quiescent current demand drops to the levels
specified in Table 79. The FPGA does not use or require the
surplus current to successfully power-on and configure. If
applying VCCINT before VCCAUX, ensure that the regulator
does not have a foldback feature that could inadvertently
shut down in the presence of the surplus current.
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS
configuration latches. The data in these latches is retained
even when the voltages drop to the minimum levels
necessary to preserve RAM contents, as specified in
If, after configuration, the VCCAUX or VCCINT supply drops
below its data retention voltage, the current device
configuration must be cleared using one of the following
methods:
Force the VCCAUX or VCCINT supply voltage below the
minimum Power On Reset (POR) voltage threshold
Assert PROG_B Low.
The POR circuit does not monitor the VCCO_2 supply after
configuration. Consequently, dropping the VCCO_2 voltage
does not reset the device by triggering a Power-On Reset
(POR) event.
No Internal Charge Pumps or Free-Running
Oscillators
Some system applications are sensitive to sources of
analog noise. Spartan-3E FPGA circuitry is fully static and
does not employ internal charge pumps.
The CCLK configuration clock is active during the FPGA
configuration process. After configuration completes, the
CCLK oscillator is automatically disabled unless the
Bitstream Generator (BitGen) option Persist=Yes.
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| XC3S500E-5FT256C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 500K GATES 10476 CELLS 657MHZ 90NM 1.2V 256F - Trays |
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