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參數(shù)資料
| 型號： | XC3S500E-5FGG320C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 194/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 500K 320-FBGA |
| 標準包裝： | 84 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 1164 |
| 邏輯元件/單元數(shù)： | 10476 |
| RAM 位總計： | 368640 |
| 輸入/輸出數(shù)： | 232 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 320-BGA |
| 供應商設備封裝： | 320-FBGA（19x19） |
| 配用： | 122-1536-ND - KIT STARTER SPARTAN-3E |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
69
The configuration pins also operate at other voltages by
setting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V
or 1.8V. The change on the VCCO supply also changes the
I/O characteristics, including the effective IOSTANDARD.
For example, with VCCO = 3.3V, the output characteristics
will be similar to those of LVCMOS33, and the current when
driving High, IOH, increases to approximately 12 to 16 mA,
while the current when driving Low, IOL, remains 8 mA. At
VCCO = 1.8V, the output characteristics will be similar to
those of LVCMOS18, and the current when driving High,
IOH, decreases slightly to approximately 6 to 8 mA. Again,
the current when driving Low, IOL, remains 8 mA. The
output voltages are determined by the VCCO level,
LVCMOS18 for 1.8V, LVCMOS25 for 2.5V, and LVCMOS33
for 3.3V. For more details see UG332.
CCLK Design Considerations
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
The FPGA’s configuration process is controlled by the
CCLK configuration clock. Consequently, signal integrity of
CCLK is important to guarantee successful configuration.
Poor CCLK signal integrity caused by ringing or reflections
might cause double-clocking, causing the configuration
process to fail.
Although the CCLK frequency is relatively low, Spartan-3E
FPGA output edge rates are fast. Therefore, careful
attention must be paid to the CCLK signal integrity on the
printed circuit board. Signal integrity simulation with IBIS is
recommended. For all configuration modes except JTAG,
the signal integrity must be considered at every CCLK trace
destination, including the FPGA’s CCLK pin.
This analysis is especially important when the FPGA
re-uses the CCLK pin as a user-I/O after configuration. In
these cases, there might be unrelated devices attached to
CCLK, which add additional trace length and signal
destinations.
In the Master Serial, SPI, and BPI configuration modes, the
FPGA drives the CCLK pin and CCLK should be treated as
a full bidirectional I/O pin for signal integrity analysis. In BPI
mode, CCLK is only used in multi-FPGA daisy-chains.
The best signal integrity is ensured by following these basic
PCB guidelines:
Route the CCLK signal as a 50
Ω
controlled-impedance transmission line.
Route the CCLK signal without any branching. Do not
use a “star” topology.
Keep stubs, if required, shorter than 10 mm (0.4
inches).
Terminate the end of the CCLK transmission line.
Design Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
Unlike previous Spartan FPGA families, nearly all of the
Spartan-3E dual-purpose configuration pins are available
as full-featured user I/O pins after successful configuration,
when the DONE output goes High.
The HSWAP pin, the mode select pins (M[2:0]), and the
variant-select pins (VS[2:0]) must have valid and stable
logic values at the start of configuration. VS[2:0] are only
used in the SPI configuration mode. The levels on the
M[2:0] pins and VS[2:0] pins are sampled when the INIT_B
pin returns High. See Figure 76 for a timing example.
The HSWAP pin defines whether FPGA user I/O pins have
a pull-up resistor connected to their associated VCCO
supply pin during configuration or not, as shown Table 48.
HSWAP must be valid at the start of configuration and
remain constant throughout the configuration process.
The Configuration section provides detailed schematics for
each configuration mode. The schematics indicate the
required logic values for HSWAP, M[2:0], and VS[2:0] but do
not specify how the application provides the logic Low or
High value. The HSWAP, M[2:0], and VS[2:0] pins can be
either dedicated or reused by the FPGA application.
Dedicating the HSWAP, M[2:0], and VS[2:0] Pins
If the HSWAP, M[2:0], and VS[2:0] pins are not required by
the FPGA design after configuration, simply connect these
pins directly to the VCCO or GND supply rail shown in the
appropriate configuration schematic.
Reusing HSWAP, M[2:0], and VS[2:0] After Config-
uration
To reuse the HSWAP, M[2:0], and VS[2:0] pin after
configuration, use pull-up or pull-down resistors to define
the logic values shown in the appropriate configuration
schematic.
Table 48: HSWAP Behavior
HSWAP
Value
Description
0
Pull-up resistors connect to the associated VCCO
supply for all user-I/O or dual-purpose I/O pins
during configuration. Pull-up resistors are active until
configuration completes.
1
Pull-up resistors disabled during configuration. All
user-I/O or dual-purpose I/O pins are in a
high-impedance state.
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