參數(shù)資料
型號: XC3S50A-4VQ100I
廠商: Xilinx Inc
文件頁數(shù): 71/132頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 100VQFP
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 176
邏輯元件/單元數(shù): 1584
RAM 位總計(jì): 55296
輸入/輸出數(shù): 68
門數(shù): 50000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
43
Table 31: CLB Distributed RAM Switching Characteristics
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
–1.69
–2.01
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
0.07
0.02
–ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
0.18
–0.36
–ns
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
0.30
–0.59
–ns
Hold Times
TDH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
0.13
–0.13
–ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
0.01
–0.01
–ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.88
–1.01
–ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
Table 32: CLB Shift Register Switching Characteristics
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
–4.11
–4.82
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.13
–0.18
–ns
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.16
–0.16
–ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.90
–1.01
–ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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