參數(shù)資料
型號: XC3S50AN-4TQ144I
廠商: Xilinx Inc
文件頁數(shù): 40/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3AN 144TQFP
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-3AN
LAB/CLB數(shù): 176
邏輯元件/單元數(shù): 1584
RAM 位總計: 55296
輸入/輸出數(shù): 108
門數(shù): 50000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
23
Device DNA Read Endurance
In-System Flash Memory Data Retention, Program/Write Endurance
Table 17: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations
30,000,000
Read
cycles
Table 18: In-System Flash (ISF) Memory Characteristics
Symbol
Description
Minimum(1)
Units
ISF_RETENTION
Data retention
20
Years
ISF_ACTIVE
Time that the ISF memory is selected and active. SPI_ACCESS design primitive
pins CSB = Low, CLK toggling
2
Years
ISF_PAGE_CYCLES
Number of program/erase cycles, per ISF memory page
100,000
Cycles
ISF_PAGE_REWRITE
Number of cumulative random (non-sequential) page erase/program operations
within a sector before pages must be rewritten
10,000
Cycles
ISF_SPR_CYCLES
Number of program/erase cycles for Sector Protection Register
10,000
Cycles
ISF_SEC_CYCLES
Number of program cycles for Sector Lockdown Register per sector,
user-programmable field in Security Register, and Power-of-2 Page Size
1Cycle
Notes:
1.
Minimum value at which functionality is still guaranteed. Do not exceed these values.
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