參數(shù)資料
型號： XC3S50AN-4TQ144I
廠商： Xilinx Inc
文件頁數(shù)： 62/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3AN 144TQFP
標準包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 176
邏輯元件/單元數(shù)： 1584
RAM 位總計： 55296
輸入/輸出數(shù)： 108
門數(shù)： 50000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
43
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 30 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1.
Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 11.
Use parameter values VT, RT, and VM from Table 30.
CREF is zero.
2.
Record the time to VM.
3.
Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 29) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output
Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 31 and Table 32 provide the essential SSO
guidelines. For each device/package combination, Table 31
provides the number of equivalent VCCO/GND pairs. The
equivalent number of pairs is based on characterization and
may not match the physical number of pairs. For each
output signal standard and drive strength, Table 32
recommends the maximum number of SSOs, switching in
the same direction, allowed per VCCO/GND pair within an
I/O bank. The guidelines in Table 32 are categorized by
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from Table 31 and
Table 32 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 31 x Table 32
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (TQ) is
lower than for ball grid array packages (FG) due to the
larger lead inductance of the quad-flat packages. Ball grid
array packages are recommended for applications with a
large number of simultaneously switching outputs.
Table 31: Equivalent VCCO/GND Pairs per Bank
Device
Package Style
TQG144 FTG256 FGG400 FGG484 FGG676
XC3S50AN
2
3
–
XC3S200AN
–4
–
XC3S400AN
–4
5
–
XC3S700AN
–
–5
–
XC3S1400AN
–
–6
9
相關PDF資料
PDF描述
748333-2 CONTACT, HD22 PIN, 30AU
748333-5 CONTACT, HD22 PIN, FLAU
24LC024-E/MS IC EEPROM 2KBIT 400KHZ 8MSOP
24C02CT-E/MNY IC SRL EEPROM 256KX8 V 8-TDFN
24LC08BT-E/MNY IC EEPROM 8KBIT 400KHZ 8TDFN
相關代理商/技術參數(shù)
參數(shù)描述
XC3S50AN-4TQG144C 功能描述:IC SPARTAN-3AN FPGA 50K 144TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S50AN-4TQG144CES 制造商:Xilinx 功能描述:
XC3S50AN-4TQG144I 功能描述:IC FPGA SPARTAN-3AN50K 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S50AN-4TQG144ICES 制造商:Xilinx 功能描述:
XC3S50AN-5FT256C 制造商:Xilinx 功能描述:SPARTAN3AN - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN-3AN 50K 256BGA 制造商:Xilinx 功能描述:IC FPGA 195 I/O 256FTBGA
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*