參數(shù)資料
型號(hào)： XC4VFX12-11FFG668I
廠商： Xilinx Inc
文件頁數(shù)： 21/58頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-4 FX 12K 668FCBGA
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-4 FX
LAB/CLB數(shù)： 1368
邏輯元件/單元數(shù)： 12312
RAM 位總計(jì)： 663552
輸入/輸出數(shù)： 320
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 668-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 668-FCBGA
配用： HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
28
Input Serializer/Deserializer Switching Characteristics
Table 34: ISERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
Setup/Hold for Control Lines
TISCCK_BITSLIP / TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
0.28
–0.20
0.34
–0.16
0.40
–0.13
ns
TISCCK_CE / TISCKC_CE(2)
CE pin Setup/Hold with respect to CLK (for CE1)
0.48
–0.37
0.57
–0.30
0.69
–0.25
ns
TISCCK_CE2 / TISCKC_CE2(2)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
0.11
–0.04
0.14
–0.03
0.16
–0.02
ns
TISCCK_DLYCE / TISCKC_DLYCE
DLYCE pin Setup/Hold with respect to CLKDIV
0.16
0.11
0.19
0.13
0.23
0.16
ns
TISCCK_DLYINC / TISCKC_DLYINC
DLYINC pin Setup/Hold with respect to CLKDIV
0.01
0.36
0.01
0.43
0.01
0.51
ns
TISCCK_DLYRST / TISCKC_DLYRST
DLYRST pin Setup/Hold with respect to CLKDIV
–0.03
0.37
–0.02
0.45
–0.02
0.54
ns
TISCCK_SR
SR pin Setup with respect to CLKDIV
0.64
0.77
0.92
ns
Setup/Hold for Data Lines
TISDCK_D / TISCKD_D
D pin Setup/Hold with respect to CLK
(IOBDELAY = IBUF or NONE)
0.24
–0.11
0.28
–0.11
0.34
–0.11
ns
D pin Setup/Hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
6.64
–6.51
7.63
–6.51
8.84
–6.51
ns
D pin Setup/Hold with respect to CLK(1)
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.81
–0.68
0.87
–0.68
1.08
–0.68
ns
TISDCK_DDR / TISCKD_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE)
0.24
–0.11
0.28
–0.11
0.34
–0.11
ns
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
6.64
–6.51
7.63
–6.51
8.84
–6.51
ns
D pin Setup/Hold with respect to CLK at DDR mode(1)
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.81
–0.68
0.87
–0.68
1.08
–0.68
ns
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
0.59
0.71
0.85
ns
Propagation Delays
TISDO_DO_IOBDELAY_IFD
D input to DO output pin (IOBDELAY = IFD)
0.17
0.20
0.24
ns
TISDO_DO_IOBDELAY_NONE
D input to DO output pin (IOBDELAY = NONE)
0.17
0.20
0.24
ns
TISDO_DO_IOBDELAY_BOTH
D input to DO output pin (IOBDELAY = BOTH,
IOBDELAY_TYPE = DEFAULT)
6.00
6.91
7.96
ns
D input to DO output pin(1) (IOBDELAY = BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.74
0.79
0.99
ns
TISDO_DO_IOBDELAY_IBUF
D input to DO output pin (IOBDELAY = IBUF,
IOBDELAY_TYPE = DEFAULT)
6.00
6.91
7.96
ns
D input to DO output pin(1) (IOBDELAY = IBUF,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
0.74
0.79
0.99
ns
Notes:
1.
Recorded at 0 tap value. Refer to Timing Report for other values.
2.
TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE / TISCKC_CE in TRCE report.
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