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參數(shù)資料
| 型號： | XC4VFX12-11FFG668I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 37/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-4 FX 12K 668FCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-4 FX |
| LAB/CLB數(shù)： | 1368 |
| 邏輯元件/單元數(shù)： | 12312 |
| RAM 位總計(jì)： | 663552 |
| 輸入/輸出數(shù)： | 320 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 668-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 668-FCBGA |
| 配用： | HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4 HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668 |
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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
42
Table 50: Miscellaneous Timing Parameters
Symbol
Description
Speed Grade
Units
-12
-11
-10
Time Required to Achieve LOCK
T_LOCK_DLL_240
DLL output – Frequency range > 240 MHz (2)
20
s
T_LOCK_DLL_120_240
DLL output – Frequency range 120 - 240 MHz (1,2)
63
s
T_LOCK_DLL_60_120
DLL output – Frequency range 60 - 120 MHz (1,2)
225
s
T_LOCK_DLL_50_60
DLL output – Frequency range 50 - 60 MHz(1,2)
325
s
T_LOCK_DLL_40_50
DLL output – Frequency range 40 - 50 MHz (1,2)
500
s
T_LOCK_DLL_30_40
DLL output – Frequency range 30 - 40 MHz (1,2)
900
s
T_LOCK_DLL_24_30
DLL output – Frequency range 24 - 30 MHz(1,2)
1250
s
T_LOCK_DLL_30
DLL output – Frequency range < 30 MHz (2)
1250
s
T_LOCK_FX_MAX
DFS outputs(3)
10
ms
T_LOCK_DLL_FINE_SHIFT
Multiplication factor for DLL lock time with Fine Shift
2
Fine Phase Shifting
FINE_SHIFT_RANGE_MS
Absolute shifting range in maximum speed mode
7
ns
FINE_SHIFT_RANGE_MR
Absolute shifting range in maximum range mode
10
ns
Delay Lines
DCM_TAP_MS_MIN
Tap delay resolution (Min) in maximum speed mode
5
ps
DCM_TAP_MS_MAX
Tap delay resolution (Max) in maximum speed mode
40
ps
DCM_TAP_MR_MIN
Tap delay resolution (Min) in maximum range mode
10
ps
DCM_TAP_MR_MAX
Tap delay resolution (Max) in maximum range mode
60
ps
Input Signal Requirements
DCM_RESET(4)
Minimum duration that RST must be held asserted
200
ms
Maximum duration that RST can be held asserted(5)
10
sec
DCM_INPUT_CLOCK_STOP
Maximum duration that CLKIN and CLKFB can be
stopped(6,7)
100
ms
Notes:
1.
For boundary frequencies, choose the higher delay.
2.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
3.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
4.
CLKIN must be present and stable during the DCM_RESET.
5.
This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support
of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
6.
For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped
clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support
longer durations of stopped clocks.
7.
For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4VFX12-11SF363C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 12312 CELLS 90NM 1.2V 363FCBGA - Trays |
| XC4VFX12-11SF363I | 功能描述:IC FPGA VIRTEX-4FX 363FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC4VFX12-11SFG363C | 功能描述:IC FPGA VIRTEX-4 FX 12K 363FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC4VFX12-11SFG363I | 功能描述:IC FPGA VIRTEX-4 FX 12K 363FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC4VFX12-12FF668C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 12312 CELLS 90NM 1.2V 668FCBGA - Trays |
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