參數(shù)資料
型號(hào): XC4VFX12-11FFG668I
廠商: Xilinx Inc
文件頁數(shù): 39/58頁
文件大小: 0K
描述: IC FPGA VIRTEX-4 FX 12K 668FCBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-4 FX
LAB/CLB數(shù): 1368
邏輯元件/單元數(shù): 12312
RAM 位總計(jì): 663552
輸入/輸出數(shù): 320
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 668-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 668-FCBGA
配用: HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
44
System-Synchronous Switching Characteristics
Virtex-4 FPGA Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 54. Values are expressed in nanoseconds unless otherwise noted.
Table 54: Global Clock Input to Output Delay for LVCMOS25 Standard, 12 mA, Fast Slew Rate, with DCM
Symbol
Description
Device
Speed Grade
Units
-12
-11
-10
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.
TICKOFDCM
Global Clock and OFF with DCM
XC4VLX15
2.43
2.81
3.25
ns
XC4VLX25
2.60
2.95
3.36
ns
XC4VLX40
2.54
2.91
3.32
ns
XC4VLX60
2.69
3.05
3.45
ns
XC4VLX80
2.88
3.27
3.72
ns
XC4VLX100
2.94
3.33
3.79
ns
XC4VLX160
2.94
3.35
3.82
ns
XC4VLX200
N/A
3.51
4.02
ns
XC4VSX25
2.65
2.99
3.39
ns
XC4VSX35
2.81
3.18
3.60
ns
XC4VSX55
2.83
3.20
3.62
ns
XC4VFX12
2.43
2.78
3.18
ns
XC4VFX20
2.54
2.88
3.26
ns
XC4VFX40
2.87
3.25
3.67
ns
XC4VFX60
2.92
3.31
3.77
ns
XC4VFX100
3.16
3.58
4.06
ns
XC4VFX140
N/A
3.79
4.30
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
DCM output jitter is already included in the timing calculation.
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