參數(shù)資料
型號(hào): XC4VFX12-11FFG668I
廠商: Xilinx Inc
文件頁(yè)數(shù): 44/58頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-4 FX 12K 668FCBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-4 FX
LAB/CLB數(shù): 1368
邏輯元件/單元數(shù): 12312
RAM 位總計(jì): 663552
輸入/輸出數(shù): 320
電源電壓: 1.14 V ~ 1.26 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 668-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 668-FCBGA
配用: HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
49
ChipSync Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 59: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
Speed Grade
Units
-12
-11
-10
TDCD_CLK
Global Clock Tree Duty Cycle Distortion(1)
All
150
ps
TCKSKEW
Global Clock Tree Skew(2)
XC4VLX15
50
60
ps
XC4VLX25
90
100
110
ps
XC4VLX40
140
160
180
ps
XC4VLX60
140
160
180
ps
XC4VLX80
200
230
260
ps
XC4VLX100
270
310
350
ps
XC4VLX160
270
310
350
ps
XC4VLX200
N/A
310
350
ps
XC4VSX25
50
60
70
ps
XC4VSX35
90
100
120
ps
XC4VSX55
140
170
190
ps
XC4VFX12
50
60
70
ps
XC4VFX20
60
70
ps
XC4VFX40
90
110
120
ps
XC4VFX60
140
170
190
ps
XC4VFX100
200
230
260
ps
XC4VFX140
N/A
310
350
ps
TDCD_BUFIO
I/O clock tree duty cycle distortion
All
100
ps
I/O clock tree skew across one clock region
All
50
ps
TBUFIOSKEW
I/O clock tree skew across multiple clock regions
All
50
ps
TDCD_BUFR
Regional clock tree duty cycle distortion
All
250
ps
TBUFIO_MAX_FREQ
I/O clock tree MAX frequency
All
710
645
MHz
TBUFR_MAX_FREQ
Regional clock tree MAX frequency
All
300
250
MHz
Notes:
1.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where
other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2.
The TCKSKEW value represents the worst-case vertical clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing
Analyzer tools to evaluate clock skew specific to your application.
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